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anv: Set STATE_COMPUTE_MODE mask bit when zeroing compute mode

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Justing setting all zeroes to STATE_COMPUTE_MODE will do nothing,
the mask of each register must be set for it to change.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28505>
This commit is contained in:
José Roberto de Souza 2024-03-27 09:21:03 -07:00 • committed by Marge Bot
parent ba52fb0eca
commit 2f3dc31876
2 changed files with 8 additions and 5 deletions
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9
src/intel/genxml/gen125.xml
View file

@ -1910,6 +1910,7 @@
<field name="Disable L1 Invalidate for non-L1-cacheable Writes" start="45" end="45" type="bool" />
<field name="Large GRF Mode" start="47" end="47" type="bool" />
<field name="Z Pass Async Compute Thread Limit Mask" start="48" end="50" type="uint" />
<field name="Mask1" start="48" end="63" type="uint" />
<field name="Force Non-Coherent Mask" start="51" end="52" type="uint" />
<field name="Fast Clear Disabled on Compressed Surface Mask" start="53" end="53" type="bool" />
<field name="Disable SLM Read Merge Optimization Mask" start="54" end="54" type="bool" />
@ -2129,10 +2130,10 @@
<field name="Aux Inv" start="0" end="0" type="bool" />
</register>
<register name="CCS_INSTDONE" length="1" num="0x1206c">
<field name="Ring Enable" start="0" end="0" type="bool"/>
<field name="VFE Done" start="16" end="16" type="bool"/>
<field name="TSG Done" start="17" end="17" type="bool"/>
<field name="CS Done" start="21" end="21" type="bool"/>
<field name="Ring Enable" start="0" end="0" type="bool" />
<field name="VFE Done" start="16" end="16" type="bool" />
<field name="TSG Done" start="17" end="17" type="bool" />
<field name="CS Done" start="21" end="21" type="bool" />
</register>
<register name="CHICKEN_RASTER_1" length="1" num="0x6204">
<field name="AA Line Quality Fix" start="5" end="5" type="bool" />

4
src/intel/vulkan/genX_init_state.c
View file

@ -591,7 +591,9 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch)
#endif
#if GFX_VERx10 >= 125
anv_batch_emit(&batch, GENX(STATE_COMPUTE_MODE), zero);
anv_batch_emit(&batch, GENX(STATE_COMPUTE_MODE), cm) {
cm.Mask1 = 0xffff;
}
anv_batch_emit(&batch, GENX(3DSTATE_MESH_CONTROL), zero);
anv_batch_emit(&batch, GENX(3DSTATE_TASK_CONTROL), zero);