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i965/vec4: split instructions that read 64-bit interleaved attributes
Stages that use interleaved attributes generate regions with a vstride=0 that can hit the gen7 hardware decompression bug. v2: - Make static the function and fix indent (Matt) Reviewed-by: Matt Turner <mattst88@gmail.com>
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1 changed files with 26 additions and 2 deletions
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@ -2034,6 +2034,20 @@ vec4_visitor::convert_to_hw_regs()
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}
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}
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static bool
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stage_uses_interleaved_attributes(unsigned stage,
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enum shader_dispatch_mode dispatch_mode)
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{
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switch (stage) {
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case MESA_SHADER_TESS_EVAL:
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return true;
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case MESA_SHADER_GEOMETRY:
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return dispatch_mode != DISPATCH_MODE_4X2_DUAL_OBJECT;
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default:
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return false;
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}
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}
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/**
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* Get the closest native SIMD width supported by the hardware for instruction
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* \p inst. The instruction will be left untouched by
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@ -2042,7 +2056,8 @@ vec4_visitor::convert_to_hw_regs()
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*/
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static unsigned
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get_lowered_simd_width(const struct gen_device_info *devinfo,
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const vec4_instruction *inst)
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enum shader_dispatch_mode dispatch_mode,
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unsigned stage, const vec4_instruction *inst)
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{
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/* Do not split some instructions that require special handling */
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switch (inst->opcode) {
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@ -2077,6 +2092,14 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
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continue;
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if (inst->size_read(i) <= REG_SIZE)
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lowered_width = MIN2(lowered_width, 4);
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/* Interleaved attribute setups use a vertical stride of 0, which
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* makes them hit the associated instruction decompression bug in gen7.
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* Split them to prevent this.
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*/
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if (inst->src[i].file == ATTR &&
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stage_uses_interleaved_attributes(stage, dispatch_mode))
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lowered_width = MIN2(lowered_width, 4);
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}
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}
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@ -2118,7 +2141,8 @@ vec4_visitor::lower_simd_width()
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bool progress = false;
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foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
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const unsigned lowered_width = get_lowered_simd_width(devinfo, inst);
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const unsigned lowered_width =
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get_lowered_simd_width(devinfo, prog_data->dispatch_mode, stage, inst);
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assert(lowered_width <= inst->exec_size);
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if (lowered_width == inst->exec_size)
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continue;
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