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radv: ignore pColorBlendState if rasterization is disabled
Or if the subpass has no color attachments. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167>
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1 changed files with 21 additions and 5 deletions
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@ -123,6 +123,18 @@ radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreat
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return NULL;
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}
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static const VkPipelineColorBlendStateCreateInfo *
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radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
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{
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RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
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struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
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if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
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subpass->has_color_att)
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return pCreateInfo->pColorBlendState;
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return NULL;
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}
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bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
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{
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struct radv_shader_variant *variant = NULL;
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@ -730,7 +742,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *pCreateInfo,
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const struct radv_graphics_pipeline_create_info *extra)
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{
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const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
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const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
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const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
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struct radv_blend_state blend = {0};
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unsigned mode = V_028808_CB_NORMAL;
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@ -1024,13 +1036,14 @@ radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
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RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
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struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
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const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
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const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
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unsigned colormask = blend->cb_target_enabled_4bit;
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if (!pipeline->device->physical_device->out_of_order_rast_allowed)
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return false;
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/* Be conservative if a logic operation is enabled with color buffers. */
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if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
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if (colormask && vkblend && vkblend->logicOpEnable)
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return false;
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/* Default depth/stencil invariance when no attachment is bound. */
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@ -3225,7 +3238,8 @@ radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipel
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unsigned effective_samples = total_samples;
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unsigned color_bytes_per_pixel = 0;
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const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
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const VkPipelineColorBlendStateCreateInfo *vkblend =
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radv_pipeline_get_color_blend_state(pCreateInfo);
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if (vkblend) {
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for (unsigned i = 0; i < subpass->color_count; i++) {
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if (!vkblend->pAttachments[i].colorWriteMask)
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@ -3296,7 +3310,8 @@ radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipe
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unsigned color_bytes_per_pixel = 0;
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unsigned fmask_bytes_per_pixel = 0;
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const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
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const VkPipelineColorBlendStateCreateInfo *vkblend =
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radv_pipeline_get_color_blend_state(pCreateInfo);
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if (vkblend) {
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for (unsigned i = 0; i < subpass->color_count; i++) {
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if (!vkblend->pAttachments[i].colorWriteMask)
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@ -3373,7 +3388,8 @@ radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
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if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
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RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
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struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
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const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
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const VkPipelineColorBlendStateCreateInfo *vkblend =
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radv_pipeline_get_color_blend_state(pCreateInfo);
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unsigned min_bytes_per_pixel = 0;
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if (vkblend) {
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