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nvc0: always emit a full shader colormask

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Indications are that if the colormask indicates a single bit set on
fermi, that value will always be read from $r0 instead of a potentially
higher register (if e.g. green is set). Not to upset the counting logic,
always set the header up with a full color mask for each RT. Such a
situation can basically only ever happen with generated blit shaders.

Fixes the following piglit on Fermi (Kepler is unaffected):
  fbo-stencil blit GL_DEPTH32F_STENCIL8

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 39df725f73)
This commit is contained in:
Ilia Mirkin 2015-09-06 04:51:29 -04:00 • committed by Emil Velikov
parent 3fa83e99de
commit 2ecfc4e38d
1 changed files with 1 additions and 1 deletions
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src/gallium/drivers/nouveau/nvc0/nvc0_program.c
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@ -459,7 +459,7 @@ nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
for (i = 0; i < info->numOutputs; ++i) {
if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
fp->hdr[18] |= 0xf << info->out[i].slot[0];
}
fp->fp.early_z = info->prop.fp.earlyFragTests;