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freedreno: Use threadsize calculated by ir3

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9498>
This commit is contained in:
Connor Abbott 2021-03-10 13:42:47 +01:00 • committed by Marge Bot
parent 7ecc70b31c
commit 2ecb9700e8
5 changed files with 8 additions and 19 deletions
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2
src/gallium/drivers/freedreno/a4xx/fd4_program.c
View file

@ -176,7 +176,7 @@ fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit,
setup_stages(emit, s);
fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
fssz = (s[FS].i->double_threadsize) ? FOUR_QUADS : TWO_QUADS;
/* blob seems to always use constmode currently: */
constmode = 1;

17
src/gallium/drivers/freedreno/a5xx/fd5_compute.c
View file

@ -35,12 +35,10 @@
/* maybe move to fd5_program? */
static void
cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v,
const struct pipe_grid_info *info)
cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v)
{
const unsigned *local_size = info->block;
const struct ir3_info *i = &v->info;
enum a3xx_threadsize thrsz;
enum a3xx_threadsize thrsz = i->double_threadsize ? FOUR_QUADS : TWO_QUADS;
unsigned instrlen = v->instrlen;
/* if shader is more than 32*16 instructions, don't preload it. Similar
@ -49,15 +47,6 @@ cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v,
if (instrlen > 32)
instrlen = 0;
/* maybe the limit should be 1024.. basically if we can't have full
* occupancy, use TWO_QUAD mode to reduce divergence penalty.
*/
if ((local_size[0] * local_size[1] * local_size[2]) < 512) {
thrsz = TWO_QUADS;
} else {
thrsz = FOUR_QUADS;
}
OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
OUT_RING(ring, 0x00000000); /* SP_SP_CNTL */
@ -128,7 +117,7 @@ fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
return;
if (ctx->dirty_shader[PIPE_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
cs_program_emit(ring, v, info);
cs_program_emit(ring, v);
fd5_emit_cs_state(ctx, ring, v);
fd5_emit_cs_consts(v, ring, ctx, info);

2
src/gallium/drivers/freedreno/a5xx/fd5_program.c
View file

@ -249,7 +249,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
bool do_streamout = (s[VS].v->shader->stream_output.num_outputs > 0);
fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
fssz = (s[FS].i->double_threadsize) ? FOUR_QUADS : TWO_QUADS;
pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);

2
src/gallium/drivers/freedreno/a6xx/fd6_compute.c
View file

@ -44,7 +44,7 @@ cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
struct ir3_shader_variant *v) assert_dt
{
const struct ir3_info *i = &v->info;
enum a6xx_threadsize thrsz = THREAD128;
enum a6xx_threadsize thrsz = i->double_threadsize ? THREAD128 : THREAD64;
OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(
.vs_state = true,

4
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View file

@ -332,7 +332,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
bool sample_shading = fs->per_samp | key->sample_shading;
fssz = THREAD128;
fssz = fs->info.double_threadsize ? THREAD128 : THREAD64;
pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
@ -709,7 +709,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
OUT_RING(ring, 0xfc); /* XXX */
OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL_0, 1);
OUT_RING(ring, A6XX_HLSQ_FS_CNTL_0_THREADSIZE(THREAD128) |
OUT_RING(ring, A6XX_HLSQ_FS_CNTL_0_THREADSIZE(fssz) |
COND(enable_varyings, A6XX_HLSQ_FS_CNTL_0_VARYINGS));
OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);