From 2eae2a6f0ecdfd91eff78121bd42fe12aa982030 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Mon, 9 Oct 2017 20:42:59 -0400 Subject: [PATCH] nv50/ir: fix 64-bit integer shifts TGSI was adjusted to always pass in 64-bit integers but nouveau was left with the old semantics. Update to the new thing. Fixes: d10fbe5159 (st/glsl_to_tgsi: fix 64-bit integer bit shifts) Reported-by: Karol Herbst Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit ce6da2a02632cc81373b5e26881c02872e80c30b) --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp index b98015a6389..aa45b810fd6 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp @@ -4090,7 +4090,9 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) tmp[0] = fetchSrc(0, c); tmp[1] = fetchSrc(0, c + 1); mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]); - src1 = fetchSrc(1, c / 2); + // Theoretically src1 is a 64-bit value but in practice only the low + // bits matter. The IR expects this to be a 32-bit value. + src1 = fetchSrc(1, c); mkOp2(op, dstTy, dst, src0, src1); mkSplit(&dst0[c], 4, dst); c++;