diff --git a/.pick_status.json b/.pick_status.json
index f498e87b4a7..45c5b49616d 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -634,7 +634,7 @@
         "description": "brw: fix shuffle with scalar/uniform index",
         "nominated": true,
         "nomination_type": 2,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "1b24612c570727a0c637159eeebbd88e79715435",
         "notes": null
diff --git a/src/intel/compiler/brw_generator.cpp b/src/intel/compiler/brw_generator.cpp
index b307882ecc9..a38293b18fe 100644
--- a/src/intel/compiler/brw_generator.cpp
+++ b/src/intel/compiler/brw_generator.cpp
@@ -379,7 +379,8 @@ brw_generator::generate_shuffle(fs_inst *inst,
          /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
          struct brw_reg addr = vec8(brw_address_reg(0));
 
-         struct brw_reg group_idx = suboffset(idx, group);
+         struct brw_reg group_idx = idx.is_scalar || is_uniform(idx) ?
+            component(idx, 0) : suboffset(idx, group);
 
          if (lower_width == 8 && group_idx.width == BRW_WIDTH_16) {
             /* Things get grumpy if the register is too wide. */