From 2e53c69d886c2a0a4d4f87f42327593bb2086bd7 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 24 May 2022 11:58:16 +0200 Subject: [PATCH] radv: move streamout_shader to radv_graphics_pipeline MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 4 ++-- src/amd/vulkan/radv_pipeline.c | 8 ++++---- src/amd/vulkan/radv_private.h | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 795999e9064..8f972003f11 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -8924,7 +8924,7 @@ radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer) { struct radv_streamout_state *so = &cmd_buffer->state.streamout; struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; - struct radv_shader_info *info = &pipeline->base.streamout_shader->info; + struct radv_shader_info *info = &pipeline->streamout_shader->info; struct radeon_cmdbuf *cs = cmd_buffer->cs; radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2); @@ -9004,7 +9004,7 @@ radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer, uint32_t firstCoun struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings; struct radv_streamout_state *so = &cmd_buffer->state.streamout; struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; - struct radv_shader_info *info = &pipeline->base.streamout_shader->info; + struct radv_shader_info *info = &pipeline->streamout_shader->info; struct radeon_cmdbuf *cs = cmd_buffer->cs; radv_flush_vgt_streamout(cmd_buffer); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index c77802d80de..7f49541d582 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -6398,7 +6398,7 @@ radv_pipeline_emit_vgt_shader_config(struct radeon_cmdbuf *ctx_cs, if (radv_pipeline_has_ngg(pipeline)) { stages |= S_028B54_PRIMGEN_EN(1); - if (pipeline->base.streamout_shader) + if (pipeline->streamout_shader) stages |= S_028B54_NGG_WAVE_ID_EN(1); if (radv_pipeline_has_ngg_passthrough(pipeline)) stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1); @@ -6700,12 +6700,12 @@ radv_pipeline_init_vertex_input_state(struct radv_graphics_pipeline *pipeline, } static struct radv_shader * -radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline) +radv_pipeline_get_streamout_shader(struct radv_graphics_pipeline *pipeline) { int i; for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) { - struct radv_shader *shader = radv_get_shader(pipeline, i); + struct radv_shader *shader = radv_get_shader(&pipeline->base, i); if (shader && shader->info.so.num_outputs > 0) return shader; @@ -6945,7 +6945,7 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv radv_pipeline_init_scratch(device, &pipeline->base); /* Find the last vertex shader stage that eventually uses streamout. */ - pipeline->base.streamout_shader = radv_pipeline_get_streamout_shader(&pipeline->base); + pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline); pipeline->is_ngg = radv_pipeline_has_ngg(pipeline); pipeline->has_ngg_culling = diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index c47c3140a18..724efd61678 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1948,9 +1948,6 @@ struct radv_pipeline { unsigned max_waves; unsigned scratch_bytes_per_wave; - /* Not NULL if graphics pipeline uses streamout. */ - struct radv_shader *streamout_shader; - /* Unique pipeline hash identifier. */ uint64_t pipeline_hash; @@ -2012,6 +2009,9 @@ struct radv_graphics_pipeline { /* Whether the pipeline uses NGG (GFX10+). */ bool is_ngg; bool has_ngg_culling; + + /* Not NULL if graphics pipeline uses streamout. */ + struct radv_shader *streamout_shader; }; struct radv_compute_pipeline {