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i965: Move intel_context::has_llc to brw_context.

Browse source 
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
This commit is contained in:
Kenneth Graunke 2013-07-06 00:20:25 -07:00
parent 794de2f387
commit 2e26afb37b
6 changed files with 7 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -884,6 +884,7 @@ struct brw_context
bool has_hiz;
bool has_separate_stencil;
bool must_use_separate_stencil;
bool has_llc;
bool has_swizzling;
bool has_surface_tile_offset;
bool has_compr4;

7
src/mesa/drivers/dri/i965/intel_batchbuffer.c
View file

@ -71,7 +71,7 @@ intel_batchbuffer_init(struct brw_context *brw)
4096, 4096);
}
if (!intel->has_llc) {
if (!brw->has_llc) {
brw->batch.cpu_map = malloc(BATCH_SZ);
brw->batch.map = brw->batch.cpu_map;
}
@ -80,7 +80,6 @@ intel_batchbuffer_init(struct brw_context *brw)
static void
intel_batchbuffer_reset(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
if (brw->batch.last_bo != NULL) {
drm_intel_bo_unreference(brw->batch.last_bo);
brw->batch.last_bo = NULL;
@ -91,7 +90,7 @@ intel_batchbuffer_reset(struct brw_context *brw)
brw->batch.bo = drm_intel_bo_alloc(brw->bufmgr, "batchbuffer",
BATCH_SZ, 4096);
if (intel->has_llc) {
if (brw->has_llc) {
drm_intel_bo_map(brw->batch.bo, true);
brw->batch.map = brw->batch.bo->virtual;
}
@ -181,7 +180,7 @@ do_flush_locked(struct brw_context *brw)
struct intel_batchbuffer *batch = &brw->batch;
int ret = 0;
if (intel->has_llc) {
if (brw->has_llc) {
drm_intel_bo_unmap(batch->bo);
} else {
ret = drm_intel_bo_subdata(batch->bo, 0, 4*batch->used, batch->map);

2
src/mesa/drivers/dri/i965/intel_context.c
View file

@ -498,7 +498,7 @@ intelInitContext(struct brw_context *brw,
brw->has_separate_stencil = brw->intelScreen->hw_has_separate_stencil;
brw->must_use_separate_stencil = brw->intelScreen->hw_must_use_separate_stencil;
brw->has_hiz = intel->gen >= 6;
intel->has_llc = brw->intelScreen->hw_has_llc;
brw->has_llc = brw->intelScreen->hw_has_llc;
brw->has_swizzling = brw->intelScreen->hw_has_swizzling;
memset(&ctx->TextureFormatSupported,

1
src/mesa/drivers/dri/i965/intel_context.h
View file

@ -118,7 +118,6 @@ struct intel_context
*/
int gen;
int gt;
bool has_llc;
};
/**

2
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View file

@ -2130,7 +2130,7 @@ intel_miptree_map_singlesample(struct brw_context *brw,
intel_miptree_map_depthstencil(brw, mt, map, level, slice);
}
/* See intel_miptree_blit() for details on the 32k pitch limit. */
else if (intel->has_llc &&
else if (brw->has_llc &&
!(mode & GL_MAP_WRITE_BIT) &&
!mt->compressed &&
(mt->region->tiling == I915_TILING_X ||

3
src/mesa/drivers/dri/i965/intel_tex_subimage.c
View file

@ -170,7 +170,6 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
bool for_glTexImage)
{
struct brw_context *brw = brw_context(ctx);
struct intel_context *intel = intel_context(ctx);
struct intel_texture_image *image = intel_texture_image(texImage);
/* The miptree's buffer. */
@ -182,7 +181,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
* a 2D BGRA texture. It could be generalized to support more types by
* varying the arithmetic loop below.
*/
if (!intel->has_llc ||
if (!brw->has_llc ||
format != GL_BGRA ||
type != GL_UNSIGNED_BYTE ||
texImage->TexFormat != MESA_FORMAT_ARGB8888 ||