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radeonsi: add support for Vega20

Browse source 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák 2017-11-07 02:02:21 +01:00
parent e8dc3c0c36
commit 2e0b00ab7d
12 changed files with 26 additions and 3 deletions
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7
include/pci_ids/radeonsi_pci_ids.h
View file

@ -235,4 +235,11 @@ CHIPSET(0x69A2, VEGA12)
CHIPSET(0x69A3, VEGA12)
CHIPSET(0x69AF, VEGA12)
CHIPSET(0x66A0, VEGA20)
CHIPSET(0x66A1, VEGA20)
CHIPSET(0x66A2, VEGA20)
CHIPSET(0x66A3, VEGA20)
CHIPSET(0x66A7, VEGA20)
CHIPSET(0x66AF, VEGA20)
CHIPSET(0x15DD, RAVEN)

2
src/amd/addrlib/amdgpu_asic_addr.h
View file

@ -87,6 +87,7 @@
#define AMDGPU_VEGA10_RANGE 0x01, 0x14
#define AMDGPU_VEGA12_RANGE 0x14, 0x28
#define AMDGPU_VEGA20_RANGE 0x28, 0xFF
#define AMDGPU_RAVEN_RANGE 0x01, 0x81
@ -128,6 +129,7 @@
#define ASICREV_IS_VEGA10_P(r) ASICREV_IS(r, VEGA10)
#define ASICREV_IS_VEGA12_P(r) ASICREV_IS(r, VEGA12)
#define ASICREV_IS_VEGA12_p(r) ASICREV_IS(r, VEGA12)
#define ASICREV_IS_VEGA20_P(r) ASICREV_IS(r, VEGA20)
#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)

3
src/amd/addrlib/gfx9/gfx9addrlib.cpp
View file

@ -1230,6 +1230,7 @@ BOOL_32 Gfx9Lib::HwlInitGlobalParams(
{
ADDR_ASSERT(m_settings.isVega10 == FALSE);
ADDR_ASSERT(m_settings.isRaven == FALSE);
ADDR_ASSERT(m_settings.isVega20 == FALSE);
if (m_settings.isVega12)
{
@ -1273,7 +1274,7 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
m_settings.isArcticIsland = 1;
m_settings.isVega10 = ASICREV_IS_VEGA10_P(uChipRevision);
m_settings.isVega12 = ASICREV_IS_VEGA12_P(uChipRevision);
m_settings.isVega20 = ASICREV_IS_VEGA20_P(uChipRevision);
m_settings.isDce12 = 1;
if (m_settings.isVega10 == 0)

1
src/amd/addrlib/gfx9/gfx9addrlib.h
View file

@ -56,6 +56,7 @@ struct Gfx9ChipSettings
UINT_32 isVega10 : 1;
UINT_32 isRaven : 1;
UINT_32 isVega12 : 1;
UINT_32 isVega20 : 1;
// Display engine IP version name
UINT_32 isDce12 : 1;

4
src/amd/common/ac_llvm_util.c
View file

@ -128,6 +128,8 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
return "gfx902";
case CHIP_VEGA12:
return HAVE_LLVM >= 0x0700 ? "gfx904" : "gfx902";
case CHIP_VEGA20:
return HAVE_LLVM >= 0x0700 ? "gfx906" : "gfx902";
default:
return "";
}
@ -141,7 +143,7 @@ static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
char features[256];
const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? "amdgcn-mesa-mesa3d" : "amdgcn--";
LLVMTargetRef target = ac_get_llvm_target(triple);
bool barrier_does_waitcnt = true; /* TODO: not for Vega20 */
bool barrier_does_waitcnt = family != CHIP_VEGA20;
snprintf(features, sizeof(features),
"+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s%s",

4
src/amd/common/ac_surface.c
View file

@ -143,6 +143,10 @@ static void addrlib_family_rev_id(enum radeon_family family,
*addrlib_family = FAMILY_AI;
*addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
break;
case CHIP_VEGA20:
*addrlib_family = FAMILY_AI;
*addrlib_revid = get_first(AMDGPU_VEGA20_RANGE);
break;
case CHIP_RAVEN:
*addrlib_family = FAMILY_RV;
*addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);

1
src/amd/common/amd_family.h
View file

@ -95,6 +95,7 @@ enum radeon_family {
CHIP_VEGAM,
CHIP_VEGA10,
CHIP_VEGA12,
CHIP_VEGA20,
CHIP_RAVEN,
CHIP_LAST,
};

1
src/amd/common/gfx9d.h
View file

@ -5764,6 +5764,7 @@
#define S_02883C_USE_PROVOKING_ZW(x) (((unsigned)(x) & 0x1) << 4)
#define G_02883C_USE_PROVOKING_ZW(x) (((x) >> 4) & 0x1)
#define C_02883C_USE_PROVOKING_ZW 0xFFFFFFEF
#define R_028840_PA_STEREO_CNTL 0x028840
#define R_028A00_PA_SU_POINT_SIZE 0x028A00
#define S_028A00_HEIGHT(x) (((unsigned)(x) & 0xFFFF) << 0)
#define G_028A00_HEIGHT(x) (((x) >> 0) & 0xFFFF)

1
src/gallium/drivers/radeonsi/si_get.c
View file

@ -78,6 +78,7 @@ const char *si_get_family_name(const struct si_screen *sscreen)
case CHIP_VEGAM: return "AMD VEGAM";
case CHIP_VEGA10: return "AMD VEGA10";
case CHIP_VEGA12: return "AMD VEGA12";
case CHIP_VEGA20: return "AMD VEGA20";
case CHIP_RAVEN: return "AMD RAVEN";
default: return "AMD unknown";
}

3
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -892,7 +892,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
unsigned max_offchip_buffers_per_se;
/* Only certain chips can use the maximum value. */
if (sscreen->info.family == CHIP_VEGA12)
if (sscreen->info.family == CHIP_VEGA12 ||
sscreen->info.family == CHIP_VEGA20)
max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
else
max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;

1
src/gallium/drivers/radeonsi/si_state.c
View file

@ -4992,6 +4992,7 @@ static void si_init_config(struct si_context *sctx)
switch (sctx->family) {
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
pc_lines = 4096;
break;
case CHIP_RAVEN:

1
src/gallium/drivers/radeonsi/si_state_binning.c
View file

@ -401,6 +401,7 @@ void si_emit_dpbb_state(struct si_context *sctx)
switch (sctx->family) {
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
case CHIP_RAVEN:
/* Tuned for Raven. Vega might need different values. */
context_states_per_bin = 5;