From 2dedd8dbb2dbddd9ad6acb45248bcb62ab47d0f3 Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Fri, 15 Nov 2024 16:54:41 -0500 Subject: [PATCH] intel/isl: Fix DecompressInL3 assignment on gfx12.5 * In the ACM PRMs, the programming notes under RENDER_SURFACE_STATE::MemoryCompressionEnable state that the DecompressInL3 bit must be set for media compression. * Unlike TGL, ACM seems to handle format reinterpretation just fine without using the bit. Update the assignment accordingly. Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/isl/isl_surface_state.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index e025a4b4403..68fbaa8479b 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -763,7 +763,14 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif #if GFX_VER == 12 s.MemoryCompressionEnable = info->aux_usage == ISL_AUX_USAGE_MC; - +#endif +#if GFX_VERx10 == 125 + /* In the ACM PRMs, the programming notes under + * RENDER_SURFACE_STATE::MemoryCompressionEnable state that the + * following bit must be set for media compression. + */ + s.DecompressInL3 = info->aux_usage == ISL_AUX_USAGE_MC; +#elif GFX_VERx10 == 120 /* The Tiger Lake PRM for RENDER_SURFACE_STATE::DecompressInL3 says: * * When this field is set to 1h, the associated compressible surface,