fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-25 06:30:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965/blorp: Refactor to get rid of the get_wm_prog virtual function

Browse source 
Instead of having a virtual member function for getting the WM/PS kernel,
we simply add fields for prog_data and the kernel to brw_blorp_parms and
always make sure those get set as part of the different constructors.

v2: Use use prog_data != NULL to check for a valid program instead of a
    magic kernel offset value

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand 2016-04-22 11:38:23 -07:00
parent 18d1658633
commit 2dda4ff014
7 changed files with 58 additions and 97 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
src/mesa/drivers/dri/i965/brw_blorp.cpp
View file

@ -165,10 +165,11 @@ brw_blorp_params::brw_blorp_params(unsigned num_varyings,
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
fast_clear_op(0),
use_wm_prog(false),
num_varyings(num_varyings),
num_draw_buffers(num_draw_buffers),
num_layers(num_layers)
num_layers(num_layers),
wm_prog_kernel(0),
wm_prog_data(NULL)
{
color_write_disable[0] = false;
color_write_disable[1] = false;
@ -352,10 +353,3 @@ brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
default: unreachable("not reached");
}
}
uint32_t
brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const
{
return 0;
}

13
src/mesa/drivers/dri/i965/brw_blorp.h
View file

@ -229,7 +229,6 @@ struct brw_blorp_prog_data
bool persample_msaa_dispatch;
};
class brw_blorp_params
{
public:
@ -237,9 +236,6 @@ public:
unsigned num_draw_buffers = 1,
unsigned num_layers = 1);
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const = 0;
uint32_t x0;
uint32_t y0;
uint32_t x1;
@ -251,11 +247,12 @@ public:
enum gen6_hiz_op hiz_op;
unsigned fast_clear_op;
bool color_write_disable[4];
bool use_wm_prog;
brw_blorp_wm_push_constants wm_push_consts;
const unsigned num_varyings;
const unsigned num_draw_buffers;
const unsigned num_layers;
uint32_t wm_prog_kernel;
struct brw_blorp_prog_data *wm_prog_data;
};
@ -288,9 +285,6 @@ public:
brw_hiz_op_params(struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer,
gen6_hiz_op op);
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const;
};
struct brw_blorp_blit_prog_key
@ -388,9 +382,6 @@ public:
GLfloat dst_x1, GLfloat dst_y1,
GLenum filter, bool mirror_x, bool mirror_y);
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const;
private:
brw_blorp_blit_prog_key wm_prog_key;
};

12
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
View file

@ -1967,7 +1967,6 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
src.brw_surfaceformat = dst.brw_surfaceformat;
}
use_wm_prog = true;
memset(&wm_prog_key, 0, sizeof(wm_prog_key));
/* texture_data_type indicates the register type that should be used to
@ -2203,16 +2202,10 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
src.x_offset *= 2;
src.y_offset /= 2;
}
}
uint32_t
brw_blorp_blit_params::get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const
{
uint32_t prog_offset = 0;
if (!brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
&this->wm_prog_key, sizeof(this->wm_prog_key),
&prog_offset, prog_data)) {
&this->wm_prog_kernel, &this->wm_prog_data)) {
brw_blorp_blit_program prog(brw, &this->wm_prog_key);
GLuint program_size;
const GLuint *program = prog.compile(brw, INTEL_DEBUG & DEBUG_BLORP,
@ -2221,7 +2214,6 @@ brw_blorp_blit_params::get_wm_prog(struct brw_context *brw,
&this->wm_prog_key, sizeof(this->wm_prog_key),
program, program_size,
&prog.prog_data, sizeof(prog.prog_data),
&prog_offset, prog_data);
&this->wm_prog_kernel, &this->wm_prog_data);
}
return prog_offset;
}

50
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
View file

@ -53,9 +53,6 @@ struct brw_blorp_const_color_prog_key
class brw_blorp_const_color_params : public brw_blorp_params
{
public:
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const;
brw_blorp_const_color_prog_key wm_prog_key;
};
@ -136,6 +133,25 @@ brw_blorp_const_color_program::~brw_blorp_const_color_program()
ralloc_free(mem_ctx);
}
static void
brw_blorp_params_get_clear_kernel(struct brw_context *brw,
struct brw_blorp_params *params,
brw_blorp_const_color_prog_key *wm_prog_key)
{
if (!brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
wm_prog_key, sizeof(*wm_prog_key),
&params->wm_prog_kernel, &params->wm_prog_data)) {
brw_blorp_const_color_program prog(brw, wm_prog_key);
GLuint program_size;
const GLuint *program = prog.compile(brw, &program_size);
brw_upload_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
wm_prog_key, sizeof(*wm_prog_key),
program, program_size,
&prog.prog_data, sizeof(prog.prog_data),
&params->wm_prog_kernel, &params->wm_prog_data);
}
}
static bool
set_write_disables(const struct intel_renderbuffer *irb,
const GLubyte *color_mask, bool *color_write_disable)
@ -191,8 +207,6 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,
memcpy(&wm_push_consts.dst_x0, ctx->Color.ClearColor.f, sizeof(float) * 4);
use_wm_prog = true;
memset(&wm_prog_key, 0, sizeof(wm_prog_key));
wm_prog_key.use_simd16_replicated_data = true;
@ -223,6 +237,8 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,
} else {
brw_meta_get_buffer_rect(fb, &x0, &y0, &x1, &y1);
}
brw_blorp_params_get_clear_kernel(brw, this, &wm_prog_key);
}
@ -243,33 +259,13 @@ brw_blorp_rt_resolve_params::brw_blorp_rt_resolve_params(
* ensure that the fragment shader delivers the data using the "replicated
* color" message.
*/
use_wm_prog = true;
memset(&wm_prog_key, 0, sizeof(wm_prog_key));
wm_prog_key.use_simd16_replicated_data = true;
brw_blorp_params_get_clear_kernel(brw, this, &wm_prog_key);
}
uint32_t
brw_blorp_const_color_params::get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data)
const
{
uint32_t prog_offset = 0;
if (!brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
&this->wm_prog_key, sizeof(this->wm_prog_key),
&prog_offset, prog_data)) {
brw_blorp_const_color_program prog(brw, &this->wm_prog_key);
GLuint program_size;
const GLuint *program = prog.compile(brw, &program_size);
brw_upload_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
&this->wm_prog_key, sizeof(this->wm_prog_key),
program, program_size,
&prog.prog_data, sizeof(prog.prog_data),
&prog_offset, prog_data);
}
return prog_offset;
}
void
brw_blorp_const_color_program::alloc_regs()
{

22
src/mesa/drivers/dri/i965/gen6_blorp.cpp
View file

@ -614,10 +614,9 @@ gen6_blorp_emit_sf_config(struct brw_context *brw,
*/
static void
gen6_blorp_emit_wm_config(struct brw_context *brw,
const brw_blorp_params *params,
uint32_t prog_offset,
brw_blorp_prog_data *prog_data)
const brw_blorp_params *params)
{
const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
uint32_t dw2, dw4, dw5, dw6;
/* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
@ -650,7 +649,7 @@ gen6_blorp_emit_wm_config(struct brw_context *brw,
dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
dw6 |= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
dw6 |= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT; /* No inputs from SF */
if (params->use_wm_prog) {
if (params->wm_prog_data) {
dw4 |= prog_data->first_curbe_grf << GEN6_WM_DISPATCH_START_GRF_SHIFT_0;
dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
dw5 |= GEN6_WM_DISPATCH_ENABLE; /* We are rendering */
@ -674,7 +673,7 @@ gen6_blorp_emit_wm_config(struct brw_context *brw,
BEGIN_BATCH(9);
OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
OUT_BATCH(params->wm_prog_kernel);
OUT_BATCH(dw2);
OUT_BATCH(0); /* No scratch needed */
OUT_BATCH(dw4);
@ -977,15 +976,12 @@ void
gen6_blorp_exec(struct brw_context *brw,
const brw_blorp_params *params)
{
brw_blorp_prog_data *prog_data = NULL;
uint32_t cc_blend_state_offset = 0;
uint32_t cc_state_offset = 0;
uint32_t depthstencil_offset;
uint32_t wm_push_const_offset = 0;
uint32_t wm_bind_bo_offset = 0;
uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
/* Emit workaround flushes when we switch from drawing to blorping. */
brw_emit_post_sync_nonzero_flush(brw);
@ -998,14 +994,14 @@ gen6_blorp_exec(struct brw_context *brw,
(1 << params->dst.num_samples) - 1 : 1);
gen6_blorp_emit_vertices(brw, params);
gen6_blorp_emit_urb_config(brw, params);
if (params->use_wm_prog) {
if (params->wm_prog_data) {
cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
cc_state_offset = gen6_blorp_emit_cc_state(brw);
}
depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
gen6_blorp_emit_cc_state_pointers(brw, params, cc_blend_state_offset,
depthstencil_offset, cc_state_offset);
if (params->use_wm_prog) {
if (params->wm_prog_data) {
uint32_t wm_surf_offset_renderbuffer;
uint32_t wm_surf_offset_texture = 0;
wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
@ -1034,12 +1030,12 @@ gen6_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_gs_disable(brw, params);
gen6_blorp_emit_clip_disable(brw);
gen6_blorp_emit_sf_config(brw, params);
if (params->use_wm_prog)
if (params->wm_prog_data)
gen6_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
else
gen6_blorp_emit_constant_ps_disable(brw, params);
gen6_blorp_emit_wm_config(brw, params, prog_offset, prog_data);
if (params->use_wm_prog)
gen6_blorp_emit_wm_config(brw, params);
if (params->wm_prog_data)
gen6_blorp_emit_binding_table_pointers(brw, wm_bind_bo_offset);
gen6_blorp_emit_viewport_state(brw, params);

28
src/mesa/drivers/dri/i965/gen7_blorp.cpp
View file

@ -461,9 +461,9 @@ gen7_blorp_emit_sf_config(struct brw_context *brw,
*/
static void
gen7_blorp_emit_wm_config(struct brw_context *brw,
const brw_blorp_params *params,
brw_blorp_prog_data *prog_data)
const brw_blorp_params *params)
{
const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
uint32_t dw1 = 0, dw2 = 0;
switch (params->hiz_op) {
@ -485,7 +485,7 @@ gen7_blorp_emit_wm_config(struct brw_context *brw,
dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
if (params->use_wm_prog)
if (params->wm_prog_data)
dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
if (params->src.mt)
@ -523,10 +523,9 @@ gen7_blorp_emit_wm_config(struct brw_context *brw,
*/
static void
gen7_blorp_emit_ps_config(struct brw_context *brw,
const brw_blorp_params *params,
uint32_t prog_offset,
brw_blorp_prog_data *prog_data)
const brw_blorp_params *params)
{
const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
uint32_t dw2, dw4, dw5;
const int max_threads_shift = brw->is_haswell ?
HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
@ -544,7 +543,7 @@ gen7_blorp_emit_ps_config(struct brw_context *brw,
if (brw->is_haswell)
dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
if (params->use_wm_prog) {
if (params->wm_prog_data) {
dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
}
@ -556,7 +555,7 @@ gen7_blorp_emit_ps_config(struct brw_context *brw,
BEGIN_BATCH(8);
OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
OUT_BATCH(params->wm_prog_kernel);
OUT_BATCH(dw2);
OUT_BATCH(0);
OUT_BATCH(dw4);
@ -805,15 +804,12 @@ gen7_blorp_exec(struct brw_context *brw,
if (brw->gen >= 8)
return;
brw_blorp_prog_data *prog_data = NULL;
uint32_t cc_blend_state_offset = 0;
uint32_t cc_state_offset = 0;
uint32_t depthstencil_offset;
uint32_t wm_push_const_offset = 0;
uint32_t wm_bind_bo_offset = 0;
uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
if (brw_state_base_address.dirty.brw & brw->ctx.NewDriverState)
brw_state_base_address.emit(brw);
@ -823,7 +819,7 @@ gen7_blorp_exec(struct brw_context *brw,
(1 << params->dst.num_samples) - 1 : 1);
gen6_blorp_emit_vertices(brw, params);
gen7_blorp_emit_urb_config(brw);
if (params->use_wm_prog) {
if (params->wm_prog_data) {
cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
cc_state_offset = gen6_blorp_emit_cc_state(brw);
gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
@ -833,7 +829,7 @@ gen7_blorp_exec(struct brw_context *brw,
gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
if (brw->use_resource_streamer)
gen7_disable_hw_binding_tables(brw);
if (params->use_wm_prog) {
if (params->wm_prog_data) {
uint32_t wm_surf_offset_renderbuffer;
uint32_t wm_surf_offset_texture = 0;
wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
@ -862,8 +858,8 @@ gen7_blorp_exec(struct brw_context *brw,
gen7_blorp_emit_streamout_disable(brw);
gen6_blorp_emit_clip_disable(brw);
gen7_blorp_emit_sf_config(brw, params);
gen7_blorp_emit_wm_config(brw, params, prog_data);
if (params->use_wm_prog) {
gen7_blorp_emit_wm_config(brw, params);
if (params->wm_prog_data) {
gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
gen7_blorp_emit_constant_ps(brw, wm_push_const_offset);
} else {
@ -876,7 +872,7 @@ gen7_blorp_exec(struct brw_context *brw,
gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
}
gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
gen7_blorp_emit_ps_config(brw, params);
gen7_blorp_emit_cc_viewport(brw);
if (params->depth.mt)

18
src/mesa/drivers/dri/i965/gen8_blorp.cpp
View file

@ -368,10 +368,9 @@ gen8_blorp_emit_wm_state(struct brw_context *brw)
*/
static void
gen8_blorp_emit_ps_config(struct brw_context *brw,
const brw_blorp_params *params,
uint32_t prog_offset,
brw_blorp_prog_data *prog_data)
const brw_blorp_params *params)
{
const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
uint32_t dw3, dw5, dw6, dw7;
dw3 = dw5 = dw6 = dw7 = 0;
@ -404,7 +403,7 @@ gen8_blorp_emit_ps_config(struct brw_context *brw,
BEGIN_BATCH(12);
OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
OUT_BATCH(prog_offset);
OUT_BATCH(params->wm_prog_kernel);
OUT_BATCH(0);
OUT_BATCH(dw3);
OUT_BATCH(0);
@ -429,9 +428,9 @@ gen8_blorp_emit_ps_blend(struct brw_context *brw)
static void
gen8_blorp_emit_ps_extra(struct brw_context *brw,
const brw_blorp_params *params,
const brw_blorp_prog_data *prog_data)
const brw_blorp_params *params)
{
const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
uint32_t dw1 = 0;
dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
@ -630,11 +629,8 @@ gen8_blorp_emit_surface_states(struct brw_context *brw,
void
gen8_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
{
brw_blorp_prog_data *prog_data = NULL;
uint32_t wm_bind_bo_offset = 0;
uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
if (gen8_state_base_address.dirty.brw & brw->ctx.NewDriverState)
gen8_upload_state_base_address(brw);
@ -696,9 +692,9 @@ gen8_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
gen8_blorp_emit_sf_config(brw);
gen8_blorp_emit_ps_blend(brw);
gen8_blorp_emit_ps_extra(brw, params, prog_data);
gen8_blorp_emit_ps_extra(brw, params);
gen8_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
gen8_blorp_emit_ps_config(brw, params);
gen8_blorp_emit_depth_stencil_state(brw, params);
gen8_blorp_emit_wm_state(brw);