From 2dba5d484b29ccb8cbf624a81350668fe6decd87 Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Sat, 20 Jan 2024 13:01:43 -0800 Subject: [PATCH] intel/fs: Adjust destination register size for global atomic on Xe2+ For 16-bit data type, we are padding 16-bit and using 32-bit data type, so we need to account for the padded portion while calculating the size_written. Rework: (Rohan) - Drop unnecessary fs_builder instance Signed-off-by: Sagar Ghuge Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index cad25f7df2e..a21d859b19e 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -7796,23 +7796,30 @@ fs_nir_emit_global_atomic(nir_to_brw_state &ntb, const fs_builder &bld, srcs[A64_LOGICAL_ARG] = brw_imm_ud(op); srcs[A64_LOGICAL_ENABLE_HELPERS] = brw_imm_ud(0); + fs_inst *inst; + unsigned size_written = 0; switch (instr->def.bit_size) { case 16: { fs_reg dest32 = bld.vgrf(BRW_TYPE_UD); - bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, - retype(dest32, dest.type), - srcs, A64_LOGICAL_NUM_SRCS); + inst = bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, + retype(dest32, dest.type), + srcs, A64_LOGICAL_NUM_SRCS); + size_written = dest32.component_size(inst->exec_size); bld.MOV(retype(dest, BRW_TYPE_UW), dest32); break; } case 32: case 64: - bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, dest, - srcs, A64_LOGICAL_NUM_SRCS); + inst = bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, dest, + srcs, A64_LOGICAL_NUM_SRCS); + size_written = dest.component_size(inst->exec_size); break; default: unreachable("Unsupported bit size"); } + + assert(size_written); + inst->size_written = size_written * instr->def.num_components; } static void