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panvk/v13: Support HSR Prepass
Add an option to enable HSR Prepass. It is currently disabled by default as it might cause performance regressions for content that: - Has very simple fragment work. - Already does a ZS prepass. Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com> Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39615>
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5 changed files with 22 additions and 0 deletions
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@ -1225,6 +1225,22 @@ GENX(pan_emit_fbd)(const struct pan_fb_info *fb, unsigned layer_idx,
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cfg.internal_layer_index = layer_idx - tiler_ctx->valhall.layer_offset;
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cfg.internal_layer_index = layer_idx - tiler_ctx->valhall.layer_offset;
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cfg.frame_argument = layer_idx;
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cfg.frame_argument = layer_idx;
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#endif
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#endif
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#if PAN_ARCH >= 13
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unsigned zs_bytes_per_pixel = pan_zsbuf_bytes_per_pixel(fb);
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/* We can interleave HSR if we have space for two ZS tiles in the tile
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* buffer. */
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unsigned max_zs_tile_size_interleave =
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fb->z_tile_buf_budget >> util_logbase2_ceil(zs_bytes_per_pixel);
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bool hsr_can_interleave = fb->tile_size <= max_zs_tile_size_interleave;
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/* Enabling prepass without interleave is generally not good for
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* performance, so disable HSR in that case. */
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cfg.hsr_prepass_enable = fb->allow_hsr_prepass && hsr_can_interleave;
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cfg.hsr_prepass_interleaving_enable = hsr_can_interleave;
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cfg.hsr_prepass_filter_enable = true;
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cfg.hsr_hierarchical_optimizations_enable = true;
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#endif
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}
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}
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#if PAN_ARCH >= 6
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#if PAN_ARCH >= 6
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@ -149,6 +149,7 @@ struct pan_fb_info {
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/* Only used on Valhall */
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/* Only used on Valhall */
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bool sprite_coord_origin;
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bool sprite_coord_origin;
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bool first_provoking_vertex;
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bool first_provoking_vertex;
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bool allow_hsr_prepass;
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/* indicates whether pixel local storage is enabled */
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/* indicates whether pixel local storage is enabled */
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bool pls_enabled;
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bool pls_enabled;
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@ -50,6 +50,7 @@ static const struct debug_control panvk_debug_options[] = {
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{"no_user_mmap_sync", PANVK_DEBUG_NO_USER_MMAP_SYNC},
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{"no_user_mmap_sync", PANVK_DEBUG_NO_USER_MMAP_SYNC},
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{"coherent_before_cached", PANVK_DEBUG_COHERENT_BEFORE_CACHED},
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{"coherent_before_cached", PANVK_DEBUG_COHERENT_BEFORE_CACHED},
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{"no_extended_va_range", PANVK_DEBUG_NO_EXTENDED_VA_RANGE},
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{"no_extended_va_range", PANVK_DEBUG_NO_EXTENDED_VA_RANGE},
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{"hsr_prepass", PANVK_DEBUG_HSR_PREPASS},
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{NULL, 0},
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{NULL, 0},
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};
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};
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@ -34,6 +34,7 @@ enum panvk_debug_flags {
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PANVK_DEBUG_NO_USER_MMAP_SYNC = 1 << 15,
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PANVK_DEBUG_NO_USER_MMAP_SYNC = 1 << 15,
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PANVK_DEBUG_COHERENT_BEFORE_CACHED = 1 << 16,
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PANVK_DEBUG_COHERENT_BEFORE_CACHED = 1 << 16,
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PANVK_DEBUG_NO_EXTENDED_VA_RANGE = 1 << 17,
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PANVK_DEBUG_NO_EXTENDED_VA_RANGE = 1 << 17,
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PANVK_DEBUG_HSR_PREPASS = 1 << 17,
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};
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};
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extern uint64_t panvk_debug;
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extern uint64_t panvk_debug;
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@ -394,6 +394,9 @@ panvk_per_arch(cmd_init_render_state)(struct panvk_cmd_buffer *cmdbuf,
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.z_tile_buf_budget = pan_query_optimal_z_tib_size(PAN_ARCH, phys_dev->model),
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.z_tile_buf_budget = pan_query_optimal_z_tib_size(PAN_ARCH, phys_dev->model),
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.nr_samples = 0,
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.nr_samples = 0,
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.rt_count = pRenderingInfo->colorAttachmentCount,
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.rt_count = pRenderingInfo->colorAttachmentCount,
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#if PAN_ARCH >= 13
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.allow_hsr_prepass = PANVK_DEBUG(HSR_PREPASS),
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#endif
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};
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};
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/* In case ms2ss is enabled, use the provided sample count.
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/* In case ms2ss is enabled, use the provided sample count.
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* All attachments need to have sample count == 1 or the provided value.
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* All attachments need to have sample count == 1 or the provided value.
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