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radv/rt: Pre shift cull_mask

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This removes the need for masking the instance mask.

Totals from 14 (14.43% of 97) affected shaders:
CodeSize: 378696 -> 378308 (-0.10%); split: -0.12%, +0.02%
Instrs: 70854 -> 70855 (+0.00%); split: -0.02%, +0.02%
Latency: 1651235 -> 1651215 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 336290 -> 336285 (-0.00%); split: -0.00%, +0.00%
Copies: 9915 -> 9923 (+0.08%); split: -0.03%, +0.11%
PreSGPRs: 890 -> 896 (+0.67%)

 PERCENTAGE DELTAS Shaders  CodeSize   Instrs   Latency  InvThroughput   Copies   PreSGPRs
 q2rtx-pipe        48        -0.02%    -0.02%    -0.00%      -0.00%      -0.03%      .
 q2rtx_1           49        -0.10%    +0.02%    +0.00%      +0.00%      +0.14%    +0.31%
 -------------------------------------------------------------------------------------------
 All affected      14        -0.10%    +0.00%    -0.00%      -0.00%      +0.08%    +0.67%
 -------------------------------------------------------------------------------------------
 Total             97        -0.06%    +0.00%    -0.00%      -0.00%      +0.06%    +0.16%

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21530>
This commit is contained in:
Konstantin Seurer 2023-02-25 12:15:57 +01:00 • committed by Marge Bot
parent 964323fe97
commit 2d93ab795b
3 changed files with 10 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/amd/vulkan/radv_nir_lower_ray_queries.c
View file

@ -376,7 +376,7 @@ lower_rq_initialize(nir_builder *b, nir_ssa_def *index, nir_intrinsic_instr *ins
struct ray_query_vars *vars) struct ray_query_vars *vars)
{ {
rq_store_var(b, index, vars->flags, instr->src[2].ssa, 0x1); rq_store_var(b, index, vars->flags, instr->src[2].ssa, 0x1);
rq_store_var(b, index, vars->cull_mask, nir_iand_imm(b, instr->src[3].ssa, 0xff), 0x1); rq_store_var(b, index, vars->cull_mask, nir_ishl_imm(b, instr->src[3].ssa, 24), 0x1);
rq_store_var(b, index, vars->origin, instr->src[4].ssa, 0x7); rq_store_var(b, index, vars->origin, instr->src[4].ssa, 0x7);
rq_store_var(b, index, vars->trav.origin, instr->src[4].ssa, 0x7); rq_store_var(b, index, vars->trav.origin, instr->src[4].ssa, 0x7);

5
src/amd/vulkan/radv_rt_common.c
View file

@ -672,9 +672,8 @@ radv_build_ray_traversal(struct radv_device *device, nir_builder *b,
1); 1);
nir_ssa_def *instance_and_mask = nir_channel(b, instance_data, 2); nir_ssa_def *instance_and_mask = nir_channel(b, instance_data, 2);
nir_ssa_def *instance_mask = nir_ushr_imm(b, instance_and_mask, 24); nir_push_if(b, nir_ult(b, nir_iand(b, instance_and_mask, args->cull_mask),
nir_imm_int(b, 1 << 24)));
nir_push_if(b, nir_ieq_imm(b, nir_iand(b, instance_mask, args->cull_mask), 0));
{ {
nir_jump(b, nir_jump_continue); nir_jump(b, nir_jump_continue);
} }

13
src/amd/vulkan/radv_rt_shader.c
View file

@ -376,8 +376,8 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
/* Per the SPIR-V extension spec we have to ignore some bits for some arguments. */ /* Per the SPIR-V extension spec we have to ignore some bits for some arguments. */
nir_store_var(&b_shader, vars->accel_struct, intr->src[0].ssa, 0x1); nir_store_var(&b_shader, vars->accel_struct, intr->src[0].ssa, 0x1);
nir_store_var(&b_shader, vars->cull_mask_and_flags, nir_store_var(&b_shader, vars->cull_mask_and_flags,
nir_ior(&b_shader, nir_iand_imm(&b_shader, intr->src[2].ssa, 0xff), nir_ior(&b_shader, nir_ishl_imm(&b_shader, intr->src[2].ssa, 24),
nir_ishl_imm(&b_shader, intr->src[1].ssa, 8)), intr->src[1].ssa),
0x1); 0x1);
nir_store_var(&b_shader, vars->sbt_offset, nir_store_var(&b_shader, vars->sbt_offset,
nir_iand_imm(&b_shader, intr->src[3].ssa, 0xf), 0x1); nir_iand_imm(&b_shader, intr->src[3].ssa, 0xf), 0x1);
@ -480,7 +480,8 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
break; break;
} }
case nir_intrinsic_load_ray_flags: { case nir_intrinsic_load_ray_flags: {
ret = nir_ishr_imm(&b_shader, nir_load_var(&b_shader, vars->cull_mask_and_flags), 8); ret = nir_iand_imm(&b_shader, nir_load_var(&b_shader, vars->cull_mask_and_flags),
0xFFFFFF);
break; break;
} }
case nir_intrinsic_load_ray_hit_kind: { case nir_intrinsic_load_ray_hit_kind: {
@ -536,7 +537,7 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
} }
case nir_intrinsic_load_cull_mask: { case nir_intrinsic_load_cull_mask: {
ret = ret =
nir_iand_imm(&b_shader, nir_load_var(&b_shader, vars->cull_mask_and_flags), 0xff); nir_ishr_imm(&b_shader, nir_load_var(&b_shader, vars->cull_mask_and_flags), 24);
break; break;
} }
case nir_intrinsic_ignore_ray_intersection: { case nir_intrinsic_ignore_ray_intersection: {
@ -599,7 +600,7 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
nir_ssa_def *should_return = nir_ssa_def *should_return =
nir_test_mask(&b_shader, nir_load_var(&b_shader, vars->cull_mask_and_flags), nir_test_mask(&b_shader, nir_load_var(&b_shader, vars->cull_mask_and_flags),
SpvRayFlagsSkipClosestHitShaderKHRMask << 8); SpvRayFlagsSkipClosestHitShaderKHRMask);
if (!(vars->create_info->flags & if (!(vars->create_info->flags &
VK_PIPELINE_CREATE_RAY_TRACING_NO_NULL_CLOSEST_HIT_SHADERS_BIT_KHR)) { VK_PIPELINE_CREATE_RAY_TRACING_NO_NULL_CLOSEST_HIT_SHADERS_BIT_KHR)) {
@ -1414,7 +1415,7 @@ build_traversal_shader(struct radv_device *device,
struct radv_ray_traversal_args args = { struct radv_ray_traversal_args args = {
.root_bvh_base = root_bvh_base, .root_bvh_base = root_bvh_base,
.flags = nir_ishr_imm(&b, cull_mask_and_flags, 8), .flags = cull_mask_and_flags,
.cull_mask = cull_mask_and_flags, .cull_mask = cull_mask_and_flags,
.origin = nir_load_var(&b, vars.origin), .origin = nir_load_var(&b, vars.origin),
.tmin = nir_load_var(&b, vars.tmin), .tmin = nir_load_var(&b, vars.tmin),