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r600/sfn: Use unified code path for index register load

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Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10608>
This commit is contained in:
Gert Wollny 2021-04-30 22:08:56 +02:00
parent e9be6be49b
commit 2d8b27507d
2 changed files with 51 additions and 27 deletions
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10
src/gallium/drivers/r600/eg_sq.h
View file

@ -162,7 +162,11 @@
#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL 0x00000000
#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS 0x00000001
#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM 0x00000002
#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND_ACK 0x00000003
#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE 0x00000000
#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND 0x00000001
#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ 0x00000002
#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND 0x00000003
#define S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(x) (((unsigned)(x) & 0x7F) << 15)
#define G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(x) (((x) >> 15) & 0x7F)
#define C_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR 0xFFC07FFF
@ -567,6 +571,10 @@
/* this was clamp */
#define S_SQ_ALU_WORD1_LDS_IDX_OP_IDX_OFFSET_3(x) (((unsigned)(x) & 0x1) << 31)
#define EG_V_SQ_ALU_SRC_LDS_OQ_A_POP 0x000000DD
#define EG_V_SQ_ALU_SRC_LDS_OQ_B_POP 0x000000DE
#define V_SQ_LDS_INST_ADD 0x00
#define V_SQ_LDS_INST_SUB 0x01
#define V_SQ_LDS_INST_RSUB 0x02

68
src/gallium/drivers/r600/sfn/sfn_ir_to_assembly.cpp
View file

@ -33,7 +33,7 @@
#include "sfn_instruction_lds.h"
#include "../r600_shader.h"
#include "../r600_sq.h"
#include "../eg_sq.h"
namespace r600 {
@ -675,7 +675,7 @@ bool AssemblyFromShaderLegacyImpl::visit(const TexInstruction & tex_instr)
tex.offset_y = tex_instr.get_offset(1);
tex.offset_z = tex_instr.get_offset(2);
tex.resource_index_mode = index_mode;
tex.sampler_index_mode = tex.resource_index_mode;
tex.sampler_index_mode = index_mode;
if (tex.dst_sel_x < 4 &&
tex.dst_sel_y < 4 &&
@ -764,6 +764,7 @@ bool AssemblyFromShaderLegacyImpl::visit(const FetchInstruction& fetch_instr)
vtx.array_size = fetch_instr.array_size();
vtx.srf_mode_all = fetch_instr.srf_mode_no_zero();
if (fetch_instr.use_tc()) {
if ((r600_bytecode_add_vtx_tc(m_bc, &vtx))) {
R600_ERR("shader_from_nir: Error creating tex assembly instruction\n");
@ -796,8 +797,10 @@ bool AssemblyFromShaderLegacyImpl::visit(const EmitVertex &instr)
bool AssemblyFromShaderLegacyImpl::visit(const WaitAck& instr)
{
int r = r600_bytecode_add_cfinst(m_bc, instr.op());
if (!r)
if (!r) {
m_bc->cf_last->cf_addr = instr.n_ack();
m_bc->cf_last->barrier = 1;
}
return r == 0;
}
@ -1073,8 +1076,6 @@ AssemblyFromShaderLegacyImpl::emit_index_reg(const Value& addr, unsigned idx)
{
assert(idx < 2);
EAluOp idxop = idx ? op1_set_cf_idx1 : op1_set_cf_idx0;
if (!m_bc->index_loaded[idx] || m_loop_nesting ||
m_bc->index_reg[idx] != addr.sel()
|| m_bc->index_reg_chan[idx] != addr.chan()) {
@ -1084,29 +1085,44 @@ AssemblyFromShaderLegacyImpl::emit_index_reg(const Value& addr, unsigned idx)
if ((m_bc->cf_last->ndw>>1) >= 110)
m_bc->force_add_cf = 1;
memset(&alu, 0, sizeof(alu));
alu.op = opcode_map.at(op1_mova_int);
alu.dst.chan = 0;
alu.src[0].sel = addr.sel();
alu.src[0].chan = addr.chan();
alu.last = 1;
sfn_log << SfnLog::assembly << " mova_int, ";
int r = r600_bytecode_add_alu(m_bc, &alu);
if (r)
return bim_invalid;
if (m_bc->chip_class != CAYMAN) {
EAluOp idxop = idx ? op1_set_cf_idx1 : op1_set_cf_idx0;
memset(&alu, 0, sizeof(alu));
alu.op = opcode_map.at(op1_mova_int);
alu.dst.chan = 0;
alu.src[0].sel = addr.sel();
alu.src[0].chan = addr.chan();
alu.last = 1;
sfn_log << SfnLog::assembly << " mova_int, ";
int r = r600_bytecode_add_alu(m_bc, &alu);
if (r)
return bim_invalid;
alu.op = opcode_map.at(idxop);
alu.dst.chan = 0;
alu.src[0].sel = 0;
alu.src[0].chan = 0;
alu.last = 1;
sfn_log << SfnLog::assembly << "op1_set_cf_idx" << idx;
r = r600_bytecode_add_alu(m_bc, &alu);
if (r)
return bim_invalid;
} else {
memset(&alu, 0, sizeof(alu));
alu.op = opcode_map.at(op1_mova_int);
alu.dst.sel = idx == 0 ? CM_V_SQ_MOVA_DST_CF_IDX0 : CM_V_SQ_MOVA_DST_CF_IDX1;
alu.dst.chan = 0;
alu.src[0].sel = addr.sel();
alu.src[0].chan = addr.chan();
alu.last = 1;
sfn_log << SfnLog::assembly << " mova_int, ";
int r = r600_bytecode_add_alu(m_bc, &alu);
if (r)
return bim_invalid;
}
m_bc->ar_loaded = 0;
alu.op = opcode_map.at(idxop);
alu.dst.chan = 0;
alu.src[0].sel = 0;
alu.src[0].chan = 0;
alu.last = 1;
sfn_log << SfnLog::assembly << "op1_set_cf_idx" << idx;
r = r600_bytecode_add_alu(m_bc, &alu);
if (r)
return bim_invalid;
m_bc->index_reg[idx] = addr.sel();
m_bc->index_reg_chan[idx] = addr.chan();
m_bc->index_loaded[idx] = true;