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i965/fs: fix offset when loading double vector input varyings

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When we are not packing a double input varying, we might need to
read its data in a non-aligned to 64-bit offset, so we read
the wrong data. This is happening when using explicit locations
in varyings because Mesa disables packing varying for that case.

const_index is in 32-bit size units but offset() is multiplying
it by destination type size units. When operating with double
input varyings, const_index value could be not aligned to 64 bits.
To fix it, we load the double vector as if it was a float based vector
with twice the number of components.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
This commit is contained in:
Samuel Iglesias Gonsálvez 2016-05-26 07:56:37 +02:00
parent cb30727648
commit 2d6f82a294
1 changed files with 21 additions and 1 deletions
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22
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
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@ -3670,9 +3670,21 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
case nir_intrinsic_load_input: {
fs_reg src;
unsigned num_components = instr->num_components;
enum brw_reg_type type = dest.type;
if (stage == MESA_SHADER_VERTEX) {
src = fs_reg(ATTR, instr->const_index[0], dest.type);
} else {
assert(type_sz(type) >= 4);
if (type == BRW_REGISTER_TYPE_DF) {
/* const_index is in 32-bit type size units that could not be aligned
* with DF. We need to read the double vector as if it was a float
* vector of twice the number of components to fetch the right data.
*/
dest = retype(dest, BRW_REGISTER_TYPE_F);
num_components *= 2;
}
src = offset(retype(nir_inputs, dest.type), bld,
instr->const_index[0]);
}
@ -3681,10 +3693,18 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
assert(const_offset && "Indirect input loads not allowed");
src = offset(src, bld, const_offset->u32[0]);
for (unsigned j = 0; j < instr->num_components; j++) {
for (unsigned j = 0; j < num_components; j++) {
bld.MOV(offset(dest, bld, j), offset(src, bld, j));
}
if (type == BRW_REGISTER_TYPE_DF) {
/* Once the double vector is read, set again its original register
* type to continue with normal execution.
*/
src = retype(src, type);
dest = retype(dest, type);
}
if (type_sz(src.type) == 8) {
shuffle_32bit_load_result_to_64bit_data(bld,
dest,