diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h index 3a8b1eb939a..532c6309ab0 100644 --- a/src/freedreno/common/freedreno_dev_info.h +++ b/src/freedreno/common/freedreno_dev_info.h @@ -265,6 +265,13 @@ struct fd_dev_info { * corruption is unknown. */ bool fs_must_have_non_zero_constlen_quirk; + + /* On a740 TPL1_DBG_ECO_CNTL1.TP_UBWC_FLAG_HINT must be the same between + * all drivers in the system, somehow having different values affects + * BLIT_OP_SCALE. We cannot automatically match blob's value, so the + * best thing we could do is a toggle. + */ + bool enable_tp_ubwc_flag_hint; } a7xx; }; diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py index 45e6427ff42..441a6b6ed73 100644 --- a/src/freedreno/common/freedreno_devices.py +++ b/src/freedreno/common/freedreno_devices.py @@ -807,11 +807,13 @@ a7xx_725 = A7XXProps( cmdbuf_start_a725_quirk = True, supports_ibo_ubwc = True, fs_must_have_non_zero_constlen_quirk = True, + enable_tp_ubwc_flag_hint = True, ) a7xx_730 = A7XXProps( supports_ibo_ubwc = True, fs_must_have_non_zero_constlen_quirk = True, + enable_tp_ubwc_flag_hint = True, ) a7xx_740 = A7XXProps( @@ -820,6 +822,7 @@ a7xx_740 = A7XXProps( ubwc_unorm_snorm_int_compatible = True, supports_ibo_ubwc = True, fs_must_have_non_zero_constlen_quirk = True, + enable_tp_ubwc_flag_hint = True, ) a7xx_740_a32 = A7XXProps( @@ -829,6 +832,7 @@ a7xx_740_a32 = A7XXProps( ubwc_unorm_snorm_int_compatible = True, supports_ibo_ubwc = True, fs_must_have_non_zero_constlen_quirk = True, + enable_tp_ubwc_flag_hint = True, ) a7xx_750 = A7XXProps( diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index 90171cf8d6c..d73aedcf708 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -1269,7 +1269,17 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) if (!magic_reg.reg) break; - tu_cs_emit_write_reg(cs, magic_reg.reg, magic_reg.value); + uint32_t value = magic_reg.value; + switch(magic_reg.reg) { + case REG_A6XX_TPL1_DBG_ECO_CNTL1: + value = (value & ~A6XX_TPL1_DBG_ECO_CNTL1_TP_UBWC_FLAG_HINT) | + (phys_dev->info->a7xx.enable_tp_ubwc_flag_hint + ? A6XX_TPL1_DBG_ECO_CNTL1_TP_UBWC_FLAG_HINT + : 0); + break; + } + + tu_cs_emit_write_reg(cs, magic_reg.reg, value); } tu_cs_emit_write_reg(cs, REG_A6XX_RB_DBG_ECO_CNTL,