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intel/brw: Fix handling of cmat_signed_mask
For integer types, the signedness is determined by flags on the muladd
instruction. The types of the sources play no role. Previously we were
using the signedness of the type and ignoring the mask.
Adjust the types passed to the dpas_intel intrinsic to match.
Fixes various
dEQP-VK.compute.*.cooperative_matrix.khr_*.matrixmuladd_cross.* tests on
different Intel platforms. Some platforms had failing tests, and some
platforms failed EU validation before the tests could fail.
Fixes: 6b14da33ad ("intel/fs: nir: Add nir_intrinsic_dpas_intel")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28822>
This commit is contained in:
parent
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commit
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1 changed files with 32 additions and 2 deletions
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@ -646,14 +646,44 @@ lower_cmat_instr(nir_builder *b, nir_instr *instr, void *_state)
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const unsigned packing_factor = get_packing_factor(dst_desc, dst_slice->type);
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const unsigned num_components = glsl_get_vector_elements(dst_slice->type);
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const nir_cmat_signed cmat_signed_mask =
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nir_intrinsic_cmat_signed_mask(intrin);
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assert(((cmat_signed_mask & NIR_CMAT_A_SIGNED) == 0) ==
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((cmat_signed_mask & NIR_CMAT_B_SIGNED) == 0));
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assert(((cmat_signed_mask & NIR_CMAT_A_SIGNED) == 0) ==
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((cmat_signed_mask & NIR_CMAT_C_SIGNED) == 0));
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assert(((cmat_signed_mask & NIR_CMAT_A_SIGNED) == 0) ==
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((cmat_signed_mask & NIR_CMAT_RESULT_SIGNED) == 0));
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nir_alu_type src_type =
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nir_get_nir_type_for_glsl_base_type(src_desc.element_type);
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nir_alu_type dest_type =
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nir_get_nir_type_for_glsl_base_type(dst_desc.element_type);
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/* For integer types, the signedness is determined by flags on the
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* muladd instruction. The types of the sources play no role. Adjust the
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* types passed to the dpas_intel intrinsic to match.
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*/
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if (nir_alu_type_get_base_type(src_type) == nir_type_uint ||
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nir_alu_type_get_base_type(src_type) == nir_type_int) {
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if ((cmat_signed_mask & NIR_CMAT_A_SIGNED) == 0) {
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src_type = nir_alu_type_get_type_size(src_type) | nir_type_uint;
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dest_type = nir_alu_type_get_type_size(dest_type) | nir_type_uint;
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} else {
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src_type = nir_alu_type_get_type_size(src_type) | nir_type_int;
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dest_type = nir_alu_type_get_type_size(dest_type) | nir_type_int;
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}
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}
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nir_def *result =
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nir_dpas_intel(b,
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packing_factor * glsl_base_type_get_bit_size(dst_desc.element_type),
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nir_load_deref(b, accum_slice),
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nir_load_deref(b, A_slice),
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nir_load_deref(b, B_slice),
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.dest_type = nir_get_nir_type_for_glsl_base_type(dst_desc.element_type),
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.src_type = nir_get_nir_type_for_glsl_base_type(src_desc.element_type),
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.dest_type = dest_type,
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.src_type = src_type,
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.saturate = nir_intrinsic_saturate(intrin),
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.cmat_signed_mask = nir_intrinsic_cmat_signed_mask(intrin),
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.systolic_depth = 8,
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