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i965/fs: Add empirically-determined instruction latencies for gen7.
v2: Actually switch on the other math instructions mentioned in the
comment.
v3: Add timing data for textureSize(), and clean up some long comment
lines.
Testing shader_time of fs16 shaders on a few frames of various apps:
nexuiz improved by 2.9% +/- 1.5% (n=10)
no difference on GLB2.5 (n=36, outliers removed)
no difference on GLB2.7 (n=25)
etqw improved by 2.6% +/- 2.2% (n=25)
no difference on lightsmark (n=25)
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Eric Anholt
parent
4df1e18864
commit
2cae9f2d4a
1 changed files with 179 additions and 3 deletions
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@ -57,7 +57,7 @@ static bool debug = false;
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class schedule_node : public exec_node
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{
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public:
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schedule_node(fs_inst *inst)
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schedule_node(fs_inst *inst, int gen)
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{
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this->inst = inst;
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this->child_array_size = 0;
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@ -67,10 +67,14 @@ public:
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this->parent_count = 0;
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this->unblocked_time = 0;
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set_latency_gen4();
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if (gen >= 7)
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set_latency_gen7();
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else
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set_latency_gen4();
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}
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void set_latency_gen4();
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void set_latency_gen7();
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fs_inst *inst;
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schedule_node **children;
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@ -120,6 +124,178 @@ schedule_node::set_latency_gen4()
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}
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}
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void
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schedule_node::set_latency_gen7()
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{
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switch (inst->opcode) {
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case BRW_OPCODE_MAD:
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/* 3 cycles (this is said to be 4 cycles sometimes depending on the
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* register numbers in the sources):
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* mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q };
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*
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* 20 cycles:
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* mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q };
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* mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
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*/
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latency = 17;
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break;
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case SHADER_OPCODE_RCP:
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case SHADER_OPCODE_RSQ:
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case SHADER_OPCODE_SQRT:
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case SHADER_OPCODE_LOG2:
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case SHADER_OPCODE_EXP2:
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case SHADER_OPCODE_SIN:
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case SHADER_OPCODE_COS:
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/* 2 cycles:
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* math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
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*
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* 18 cycles:
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* math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
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* mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
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*
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* Same for exp2, log2, rsq, sqrt, sin, cos.
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*/
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latency = 16;
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break;
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case SHADER_OPCODE_POW:
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/* 2 cycles:
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* math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
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*
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* 26 cycles:
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* math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
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* mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
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*/
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latency = 24;
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break;
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case SHADER_OPCODE_TEX:
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case SHADER_OPCODE_TXD:
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case SHADER_OPCODE_TXF:
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case SHADER_OPCODE_TXL:
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/* 18 cycles:
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* mov(8) g115<1>F 0F { align1 WE_normal 1Q };
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* mov(8) g114<1>F 0F { align1 WE_normal 1Q };
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* send(8) g4<1>UW g114<8,8,1>F
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* sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
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*
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* 697 +/-49 cycles (min 610, n=26):
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* mov(8) g115<1>F 0F { align1 WE_normal 1Q };
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* mov(8) g114<1>F 0F { align1 WE_normal 1Q };
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* send(8) g4<1>UW g114<8,8,1>F
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* sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
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* mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
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*
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* So the latency on our first texture load of the batchbuffer takes
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* ~700 cycles, since the caches are cold at that point.
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*
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* 840 +/- 92 cycles (min 720, n=25):
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* mov(8) g115<1>F 0F { align1 WE_normal 1Q };
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* mov(8) g114<1>F 0F { align1 WE_normal 1Q };
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* send(8) g4<1>UW g114<8,8,1>F
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* sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
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* mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
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* send(8) g4<1>UW g114<8,8,1>F
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* sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
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* mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
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*
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* On the second load, it takes just an extra ~140 cycles, and after
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* accounting for the 14 cycles of the MOV's latency, that makes ~130.
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*
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* 683 +/- 49 cycles (min = 602, n=47):
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* mov(8) g115<1>F 0F { align1 WE_normal 1Q };
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* mov(8) g114<1>F 0F { align1 WE_normal 1Q };
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* send(8) g4<1>UW g114<8,8,1>F
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* sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
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* send(8) g50<1>UW g114<8,8,1>F
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* sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
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* mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
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*
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* The unit appears to be pipelined, since this matches up with the
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* cache-cold case, despite there being two loads here. If you replace
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* the g4 in the MOV to null with g50, it's still 693 +/- 52 (n=39).
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*
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* So, take some number between the cache-hot 140 cycles and the
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* cache-cold 700 cycles. No particular tuning was done on this.
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*
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* I haven't done significant testing of the non-TEX opcodes. TXL at
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* least looked about the same as TEX.
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*/
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latency = 200;
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break;
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case SHADER_OPCODE_TXS:
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/* Testing textureSize(sampler2D, 0), one load was 420 +/- 41
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* cycles (n=15):
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* mov(8) g114<1>UD 0D { align1 WE_normal 1Q };
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* send(8) g6<1>UW g114<8,8,1>F
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* sampler (10, 0, 10, 1) mlen 1 rlen 4 { align1 WE_normal 1Q };
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* mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1Q };
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*
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*
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* Two loads was 535 +/- 30 cycles (n=19):
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* mov(16) g114<1>UD 0D { align1 WE_normal 1H };
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* send(16) g6<1>UW g114<8,8,1>F
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* sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
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* mov(16) g114<1>UD 0D { align1 WE_normal 1H };
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* mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1H };
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* send(16) g8<1>UW g114<8,8,1>F
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* sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
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* mov(16) g8<1>F g8<8,8,1>D { align1 WE_normal 1H };
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* add(16) g6<1>F g6<8,8,1>F g8<8,8,1>F { align1 WE_normal 1H };
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*
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* Since the only caches that should matter are just the
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* instruction/state cache containing the surface state, assume that we
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* always have hot caches.
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*/
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latency = 100;
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break;
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case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
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case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
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/* testing using varying-index pull constants:
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*
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* 16 cycles:
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* mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
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* send(8) g4<1>F g4<8,8,1>D
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* data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
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*
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* ~480 cycles:
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* mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
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* send(8) g4<1>F g4<8,8,1>D
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* data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
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* mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
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*
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* ~620 cycles:
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* mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
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* send(8) g4<1>F g4<8,8,1>D
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* data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
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* mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
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* send(8) g4<1>F g4<8,8,1>D
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* data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
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* mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
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*
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* So, if it's cache-hot, it's about 140. If it's cache cold, it's
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* about 460. We expect to mostly be cache hot, so pick something more
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* in that direction.
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*/
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latency = 200;
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break;
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default:
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/* 2 cycles:
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* mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
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*
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* 16 cycles:
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* mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
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* mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
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*/
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latency = 14;
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break;
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}
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}
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class instruction_scheduler {
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public:
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instruction_scheduler(fs_visitor *v, void *mem_ctx, int grf_count,
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@ -159,7 +335,7 @@ public:
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void
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instruction_scheduler::add_inst(fs_inst *inst)
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{
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schedule_node *n = new(mem_ctx) schedule_node(inst);
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schedule_node *n = new(mem_ctx) schedule_node(inst, v->intel->gen);
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assert(!inst->is_head_sentinel());
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assert(!inst->is_tail_sentinel());
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