r600g: don't flush the gfx IB explicitly before doing DMA

It's flushed by calling r600_context_bo_reloc.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2014-03-16 19:59:50 +01:00
parent e914d0052f
commit 2c703ee8ad
4 changed files with 0 additions and 11 deletions

View file

@ -46,8 +46,6 @@ void evergreen_dma_copy(struct r600_context *rctx,
util_range_add(&rdst->valid_buffer_range, dst_offset,
dst_offset + size);
/* make sure that the dma ring is only one active */
rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
dst_offset += r600_resource_va(&rctx->screen->b.b, dst);
src_offset += r600_resource_va(&rctx->screen->b.b, src);

View file

@ -3221,9 +3221,6 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
uint64_t base, addr;
/* make sure that the dma ring is only one active */
rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
/* downcast linear aligned to linear to simplify test */

View file

@ -458,9 +458,6 @@ void r600_dma_copy(struct r600_context *rctx,
util_range_add(&rdst->valid_buffer_range, dst_offset,
dst_offset + size);
/* make sure that the dma ring is only one active */
rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
size >>= 2;
shift = 2;
ncopy = (size / 0xffff) + !!(size % 0xffff);

View file

@ -2793,9 +2793,6 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
uint64_t base, addr;
/* make sure that the dma ring is only one active */
rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
/* downcast linear aligned to linear to simplify test */