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nv50/ir: add SUQ op by reading the info from driver constbuf

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Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Ilia Mirkin 2015-12-14 00:13:34 -05:00
parent c3083c7082
commit 2c4eeb0b5c
6 changed files with 21 additions and 3 deletions
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1
src/gallium/drivers/nouveau/codegen/nv50_ir.h
View file

@ -132,6 +132,7 @@ enum operation
OP_SUBFM, // surface bitfield manipulation
OP_SUCLAMP, // clamp surface coordinates
OP_SUEAU, // surface effective address
OP_SUQ, // surface query
OP_MADSP, // special integer multiply-add
OP_TEXBAR, // texture dependency barrier
OP_DFDX,

4
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
View file

@ -3199,6 +3199,10 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
case TGSI_OPCODE_ATOMIMAX:
handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
break;
case TGSI_OPCODE_RESQ:
mkOp1(OP_SUQ, TYPE_U32, dst0[0],
makeSym(TGSI_FILE_BUFFER, tgsi.getSrc(0).getIndex(0), -1, 0, 0));
break;
case TGSI_OPCODE_IBFE:
case TGSI_OPCODE_UBFE:
FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {

11
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
View file

@ -1022,6 +1022,14 @@ NVC0LoweringPass::handleTXLQ(TexInstruction *i)
return true;
}
bool
NVC0LoweringPass::handleSUQ(Instruction *suq)
{
suq->op = OP_MOV;
suq->setSrc(0, loadResLength32(NULL, suq->getSrc(0)->reg.fileIndex * 16));
return true;
}
bool
NVC0LoweringPass::handleATOM(Instruction *atom)
{
@ -1882,6 +1890,9 @@ NVC0LoweringPass::visit(Instruction *i)
if (targ->getChipset() >= NVISA_GK104_CHIPSET)
handleSurfaceOpNVE4(i->asTex());
break;
case OP_SUQ:
handleSUQ(i);
break;
default:
break;
}

1
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
View file

@ -101,6 +101,7 @@ protected:
bool handleTXQ(TexInstruction *);
virtual bool handleManualTXD(TexInstruction *);
bool handleTXLQ(TexInstruction *);
bool handleSUQ(Instruction *);
bool handleATOM(Instruction *);
bool handleCasExch(Instruction *, bool needCctl);
void handleSurfaceOpNVE4(TexInstruction *);

1
src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
View file

@ -161,6 +161,7 @@ const char *operationStr[OP_LAST + 1] =
"subfm",
"suclamp",
"sueau",
"suq",
"madsp",
"texbar",
"dfdx",

6
src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
View file

@ -46,7 +46,7 @@ const uint8_t Target::operationSrcNr[] =
1, 1, 1, // TEX, TXB, TXL,
1, 1, 1, 1, 1, 1, 2, // TXF, TXQ, TXD, TXG, TXLQ, TEXCSAA, TEXPREP
1, 1, 2, 2, 2, 2, 2, // SULDB, SULDP, SUSTB, SUSTP, SUREDB, SUREDP, SULEA
3, 3, 3, 3, // SUBFM, SUCLAMP, SUEAU, MADSP
3, 3, 3, 1, 3, // SUBFM, SUCLAMP, SUEAU, SUQ, MADSP
0, // TEXBAR
1, 1, // DFDX, DFDY
1, 2, 1, 2, 0, 0, // RDSV, WRSV, PIXLD, QUADOP, QUADON, QUADPOP
@ -109,8 +109,8 @@ const OpClass Target::operationClass[] =
// SULDB, SULDP, SUSTB, SUSTP; SUREDB, SUREDP, SULEA
OPCLASS_SURFACE, OPCLASS_SURFACE, OPCLASS_ATOMIC, OPCLASS_SURFACE,
OPCLASS_SURFACE, OPCLASS_SURFACE, OPCLASS_SURFACE,
// SUBFM, SUCLAMP, SUEAU, MADSP
OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_ARITH,
// SUBFM, SUCLAMP, SUEAU, SUQ, MADSP
OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_ARITH,
// TEXBAR
OPCLASS_OTHER,
// DFDX, DFDY, RDSV, WRSV; PIXLD, QUADOP, QUADON, QUADPOP