diff --git a/src/freedreno/ir3/ir3_context.c b/src/freedreno/ir3/ir3_context.c
index 89137b80b33..b9d215f4e6f 100644
--- a/src/freedreno/ir3/ir3_context.c
+++ b/src/freedreno/ir3/ir3_context.c
@@ -592,6 +592,7 @@ ir3_create_array_load(struct ir3_context *ctx, struct ir3_array *arr, int n,
 	src->size  = arr->length;
 	src->array.id = arr->id;
 	src->array.offset = n;
+	src->array.base = INVALID_REG;
 
 	if (address)
 		ir3_instr_set_address(mov, address);
@@ -626,6 +627,7 @@ ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n,
 		dst->size = arr->length;
 		dst->array.id = arr->id;
 		dst->array.offset = n;
+		dst->array.base = INVALID_REG;
 
 		arr->last_write = dst;
 
@@ -653,6 +655,7 @@ ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n,
 	dst->size  = arr->length;
 	dst->array.id = arr->id;
 	dst->array.offset = n;
+	dst->array.base = INVALID_REG;
 	ir3_reg_create(mov, 0, IR3_REG_SSA | flags)->def = src->regs[0];
 
 	if (address)
diff --git a/src/freedreno/ir3/ir3_print.c b/src/freedreno/ir3/ir3_print.c
index cc099653afd..041fdf0f755 100644
--- a/src/freedreno/ir3/ir3_print.c
+++ b/src/freedreno/ir3/ir3_print.c
@@ -180,8 +180,8 @@ static void print_ssa_name(struct ir3_register *reg, bool dst)
 		print_ssa_def_name(reg);
 	}
 
-	if (reg->num != INVALID_REG)
-			printf("("SYN_REG("r%u.%c")")", reg_num(reg), "xyzw"[reg_comp(reg)]);
+	if (reg->num != INVALID_REG && !(reg->flags & IR3_REG_ARRAY))
+		printf("("SYN_REG("r%u.%c")")", reg_num(reg), "xyzw"[reg_comp(reg)]);
 }
 
 static void print_reg_name(struct ir3_instruction *instr, struct ir3_register *reg)
@@ -221,6 +221,9 @@ static void print_reg_name(struct ir3_instruction *instr, struct ir3_register *r
 			print_ssa_name(reg, false);
 		}
 		printf(SYN_ARRAY("]"));
+		if (reg->array.base != INVALID_REG)
+			printf("("SYN_REG("r%u.%c")")", reg->array.base >> 2,
+				   "xyzw"[reg->array.base & 0x3]);
 	} else if (reg->flags & IR3_REG_SSA) {
 		print_ssa_name(reg, reg->flags & IR3_REG_DEST);
 	} else if (reg->flags & IR3_REG_RELATIV) {