diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c
index b3180867a46..47dda4ec134 100644
--- a/src/compiler/nir/nir_divergence_analysis.c
+++ b/src/compiler/nir/nir_divergence_analysis.c
@@ -619,7 +619,6 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
    case nir_intrinsic_image_load:
    case nir_intrinsic_image_deref_load:
    case nir_intrinsic_bindless_image_load:
-   case nir_intrinsic_bindless_image_load_raw_nv:
    case nir_intrinsic_image_sparse_load:
    case nir_intrinsic_image_deref_sparse_load:
    case nir_intrinsic_bindless_image_sparse_load:
diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py
index afa7408dd60..9a4f75c2962 100644
--- a/src/compiler/nir/nir_intrinsics.py
+++ b/src/compiler/nir/nir_intrinsics.py
@@ -2509,7 +2509,6 @@ intrinsic("suldga_nv", dest_comp=0, src_comp=[2, 1, 1], bit_sizes=[32],
 # FLAGS is enum nak_su_ga_offset_mode
 intrinsic("sustga_nv", src_comp=[2, 1, 1, 0],
           indices=[ACCESS, FLAGS], bit_sizes=[32])
-image("load_raw_nv", src_comp=[4, 1, 1], extra_indices=[DEST_TYPE], dest_comp=0, flags=[CAN_ELIMINATE])
 # Nvidia Kepler specific load-lock store-unlock
 # used to lower shared atomics.
 intrinsic("load_shared_lock_nv", src_comp=[1], dest_comp=2)
diff --git a/src/nouveau/compiler/nak/from_nir.rs b/src/nouveau/compiler/nak/from_nir.rs
index f2b5b3c4024..a63098416f8 100644
--- a/src/nouveau/compiler/nak/from_nir.rs
+++ b/src/nouveau/compiler/nak/from_nir.rs
@@ -2683,8 +2683,7 @@ impl<'a> ShaderFromNir<'a> {
                 });
                 self.set_dst(&intrin.def, dst);
             }
-            nir_intrinsic_bindless_image_load
-            | nir_intrinsic_bindless_image_load_raw_nv => {
+            nir_intrinsic_bindless_image_load => {
                 let handle = self.get_src(&srcs[0]);
                 let dim = self.get_image_dim(intrin);
                 let coord = self.get_image_coord(intrin, dim);
@@ -2702,16 +2701,9 @@ impl<'a> ShaderFromNir<'a> {
 
                 let comps = intrin.num_components;
                 assert!(intrin.def.bit_size() == 32);
-                let image_access = if intrin.intrinsic
-                    == nir_intrinsic_bindless_image_load_raw_nv
-                {
-                    let mem_type = self.get_image_mem_type(intrin);
-                    assert!(mem_type.bits().div_ceil(32) == comps.into());
-                    ImageAccess::Binary(mem_type)
-                } else {
-                    assert!(comps == 1 || comps == 2 || comps == 4);
-                    ImageAccess::Formatted(ChannelMask::for_comps(comps))
-                };
+                assert!(comps == 1 || comps == 2 || comps == 4);
+                let image_access =
+                    ImageAccess::Formatted(ChannelMask::for_comps(comps));
 
                 let dst = b.alloc_ssa_vec(RegFile::GPR, comps);
 
diff --git a/src/nouveau/compiler/nak/ir.rs b/src/nouveau/compiler/nak/ir.rs
index c813a0dd62f..1e70cf9c73b 100644
--- a/src/nouveau/compiler/nak/ir.rs
+++ b/src/nouveau/compiler/nak/ir.rs
@@ -5057,6 +5057,7 @@ impl DisplayOp for OpTxq {
 }
 impl_display_for_op!(OpTxq);
 
+#[allow(dead_code)]
 #[derive(Clone, Copy, Eq, PartialEq)]
 pub enum ImageAccess {
     Binary(MemType),