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anv/icl: Add WA_2204188704 to disable pixel shader panic dispatch

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Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Anuj Phogat 2019-01-24 14:46:02 -08:00
parent 85ecd14ef6
commit 2be60e0c73
2 changed files with 17 additions and 0 deletions
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5
src/intel/genxml/gen11.xml
View file

@ -3681,4 +3681,9 @@
<field name="Enabled Texel Offset Precision Fix Mask" start="17" end="17" type="bool"/>
</register>
<register name="COMMON_SLICE_CHICKEN3" length="1" num="0x7304">
<field name="PS Thread Panic Dispatch" start="6" end="7" type="uint"/>
<field name="PS Thread Panic Dispatch Mask" start="22" end="23" type="uint"/>
</register>
</genxml>

12
src/intel/vulkan/genX_state.c
View file

@ -200,6 +200,18 @@ genX(init_device_state)(struct anv_device *device)
lri.DataDWord = half_slice_chicken7;
}
/* WA_2204188704: Pixel Shader Panic dispatch must be disabled.
*/
uint32_t common_slice_chicken3;
anv_pack_struct(&common_slice_chicken3, GENX(COMMON_SLICE_CHICKEN3),
.PSThreadPanicDispatch = 0x3,
.PSThreadPanicDispatchMask = 0x3);
anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
lri.RegisterOffset = GENX(COMMON_SLICE_CHICKEN3_num);
lri.DataDWord = common_slice_chicken3;
}
#endif
/* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so