From 2be01df8dfb08aaf3af349babd39dfcd5ffa74b9 Mon Sep 17 00:00:00 2001 From: Faith Ekstrand Date: Thu, 22 Feb 2024 12:31:39 -0600 Subject: [PATCH] nvk,nak: Only use u64 texture handles with codegen Reviewed-by: Mel Henning Part-of: --- src/nouveau/compiler/nak_nir_lower_tex.c | 7 +------ src/nouveau/vulkan/nvk_nir_lower_descriptors.c | 6 +++++- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/src/nouveau/compiler/nak_nir_lower_tex.c b/src/nouveau/compiler/nak_nir_lower_tex.c index 2e16c26cda8..5a8322e2400 100644 --- a/src/nouveau/compiler/nak_nir_lower_tex.c +++ b/src/nouveau/compiler/nak_nir_lower_tex.c @@ -50,7 +50,6 @@ lower_tex(nir_builder *b, nir_tex_instr *tex, const struct nak_compiler *nak) tex_h = nir_ior(b, nir_iand_imm(b, tex_h, 0x000fffff), nir_iand_imm(b, samp_h, 0xfff00000)); } - tex_h = nir_u2u32(b, tex_h); /* Array index is treated separately, so pull it off if we have one. */ nir_def *arr_idx = NULL; @@ -271,9 +270,6 @@ lower_txq(nir_builder *b, nir_tex_instr *tex, const struct nak_compiler *nak) } } - /* TODO: We should only support 32-bit handles */ - tex_h = nir_u2u32(b, tex_h); - nir_def *txq_src; nir_component_mask_t mask; switch (tex->op) { @@ -487,8 +483,7 @@ lower_image_txq(nir_builder *b, nir_intrinsic_instr *intrin, { b->cursor = nir_instr_remove(&intrin->instr); - /* TODO: We should only support 32-bit handles */ - nir_def *img_h = nir_u2u32(b, intrin->src[0].ssa); + nir_def *img_h = intrin->src[0].ssa; nir_tex_instr *txq = nir_tex_instr_create(b->shader, 1); txq->sampler_dim = remap_sampler_dim(nir_intrinsic_image_dim(intrin)); diff --git a/src/nouveau/vulkan/nvk_nir_lower_descriptors.c b/src/nouveau/vulkan/nvk_nir_lower_descriptors.c index fc1702d561c..7d8fd00a101 100644 --- a/src/nouveau/vulkan/nvk_nir_lower_descriptors.c +++ b/src/nouveau/vulkan/nvk_nir_lower_descriptors.c @@ -56,6 +56,7 @@ struct lower_descriptors_ctx { bool use_bindless_cbuf; bool use_edb_buffer_views; + bool use_nak; bool clamp_desc_array_bounds; bool indirect_bind; nir_address_format ubo_addr_format; @@ -1294,7 +1295,8 @@ lower_tex(nir_builder *b, nir_tex_instr *tex, } /* TODO: The nv50 back-end assumes it's 64-bit because of GL */ - combined_handle = nir_u2u64(b, combined_handle); + if (!ctx->use_nak) + combined_handle = nir_u2u64(b, combined_handle); /* TODO: The nv50 back-end assumes it gets handles both places, even for * texelFetch. @@ -1562,6 +1564,8 @@ nvk_nir_lower_descriptors(nir_shader *nir, .dev_info = &pdev->info, .use_bindless_cbuf = nvk_use_bindless_cbuf(&pdev->info), .use_edb_buffer_views = nvk_use_edb_buffer_views(pdev), + .use_nak = (nvk_nak_stages(&pdev->info) & + mesa_to_vk_shader_stage(nir->info.stage)) != 0, .clamp_desc_array_bounds = rs->storage_buffers != VK_PIPELINE_ROBUSTNESS_BUFFER_BEHAVIOR_DISABLED_EXT || rs->uniform_buffers != VK_PIPELINE_ROBUSTNESS_BUFFER_BEHAVIOR_DISABLED_EXT ||