diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index ad415c0c07b..3061fbdfa3b 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1211,7 +1211,9 @@ static bool use_tile_swizzle(const struct ac_surf_config *config, const struct r
 
       return surf->modifier == DRM_FORMAT_MOD_INVALID &&
              !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE |
-                              RADEON_SURF_HOST_TRANSFER)) &&
+                              RADEON_SURF_HOST_TRANSFER | RADEON_SURF_DECODE_DST |
+                              RADEON_SURF_ENCODE_SRC | RADEON_SURF_ALIASED |
+                              RADEON_SURF_REPLAYABLE)) &&
              !get_display_flag(config, surf);
    }
 }
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index d3c68a99d8d..d0383af5a25 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -75,6 +75,10 @@ enum radeon_micro_mode
 #define RADEON_SURF_PREFER_64K_ALIGNMENT  (1ull << 37)
 #define RADEON_SURF_VIDEO_REFERENCE       (1ull << 38)
 #define RADEON_SURF_HOST_TRANSFER         (1ull << 39)
+#define RADEON_SURF_DECODE_DST            (1ull << 40)
+#define RADEON_SURF_ENCODE_SRC            (1ull << 41)
+#define RADEON_SURF_ALIASED               (1ull << 42)
+#define RADEON_SURF_REPLAYABLE            (1ull << 43)
 
 struct legacy_surf_level {
    uint32_t offset_256B;   /* divided by 256, the hw can only do 40-bit addresses */
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index a95c2f3aaa8..dd3f12250af 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -718,6 +718,15 @@ radv_get_surface_flags(struct radv_device *device, struct radv_image *image, uns
        !(pCreateInfo->usage & (VK_IMAGE_USAGE_VIDEO_DECODE_DST_BIT_KHR | VK_IMAGE_USAGE_VIDEO_ENCODE_DST_BIT_KHR)))
       flags |= RADEON_SURF_VIDEO_REFERENCE;
 
+   if (pCreateInfo->usage & VK_IMAGE_USAGE_VIDEO_DECODE_DST_BIT_KHR)
+      flags |= RADEON_SURF_DECODE_DST;
+   if (pCreateInfo->usage & VK_IMAGE_USAGE_VIDEO_ENCODE_SRC_BIT_KHR)
+      flags |= RADEON_SURF_ENCODE_SRC;
+   if (pCreateInfo->flags & (VK_IMAGE_CREATE_ALIAS_BIT | VK_IMAGE_CREATE_SPARSE_ALIASED_BIT))
+      flags |= RADEON_SURF_ALIASED;
+   if (pCreateInfo->flags & VK_IMAGE_CREATE_DESCRIPTOR_BUFFER_CAPTURE_REPLAY_BIT_EXT)
+      flags |= RADEON_SURF_REPLAYABLE;
+
    if (alignment && alignment->maximumRequestedAlignment && !(instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS)) {
       bool is_4k_capable;
 
@@ -1075,10 +1084,7 @@ radv_get_ac_surf_info(struct radv_device *device, const struct radv_image *image
    info.levels = image->vk.mip_levels;
    info.num_channels = vk_format_get_nr_components(image->vk.format);
 
-   if (!image->vk.external_handle_types &&
-       !(image->vk.create_flags & (VK_IMAGE_CREATE_SPARSE_ALIASED_BIT | VK_IMAGE_CREATE_ALIAS_BIT |
-                                   VK_IMAGE_CREATE_DESCRIPTOR_BUFFER_CAPTURE_REPLAY_BIT_EXT)) &&
-       !(image->vk.usage & (VK_IMAGE_USAGE_VIDEO_DECODE_DST_BIT_KHR | VK_IMAGE_USAGE_VIDEO_ENCODE_SRC_BIT_KHR))) {
+   if (!image->vk.external_handle_types) {
       info.surf_index = &device->image_mrt_offset_counter;
       info.fmask_surf_index = &device->fmask_mrt_offset_counter;
    }