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radv: Fix shader mask for SQ_WGP SPM counters

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Signed-off-by: Josh Simmons <josh@nega.tv>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30200>
This commit is contained in:
Josh Simmons 2024-07-16 06:48:14 +02:00 • committed by Marge Bot
parent acb10043cb
commit 2b99906e5b
1 changed files with 3 additions and 3 deletions
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6
src/amd/vulkan/radv_perfcounter.c
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@ -19,10 +19,10 @@ radv_perfcounter_emit_shaders(struct radv_device *device, struct radeon_cmdbuf *
{
const struct radv_physical_device *pdev = radv_device_physical(device);
if (pdev->info.gfx_level >= GFX11) {
radeon_set_uconfig_reg(cs, R_036760_SQG_PERFCOUNTER_CTRL, shaders & 0x7f);
} else if (pdev->info.gfx_level >= GFX10) {
if (pdev->info.gfx_level >= GFX10) {
radeon_set_uconfig_reg(cs, R_036780_SQ_PERFCOUNTER_CTRL, shaders & 0x7f);
if (pdev->info.gfx_level >= GFX11)
radeon_set_uconfig_reg(cs, R_036760_SQG_PERFCOUNTER_CTRL, shaders & 0x7f);
} else {
radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2);
radeon_emit(cs, shaders & 0x7f);