diff --git a/src/nouveau/codegen/nv50_ir.h b/src/nouveau/codegen/nv50_ir.h
index fdbfec08b62..940e08403a3 100644
--- a/src/nouveau/codegen/nv50_ir.h
+++ b/src/nouveau/codegen/nv50_ir.h
@@ -95,7 +95,6 @@ enum operation
    OP_PRESIN,
    OP_PREEX2,
    OP_SQRT,
-   OP_POW,
    OP_BRA,
    OP_CALL,
    OP_RET,
diff --git a/src/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/nouveau/codegen/nv50_ir_emit_gk110.cpp
index bfba20b2b5b..9785d05e4e5 100644
--- a/src/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -2757,7 +2757,6 @@ CodeEmitterGK110::emitInstruction(Instruction *insn)
    case OP_EXP:
    case OP_LOG:
    case OP_SQRT:
-   case OP_POW:
       ERROR("operation should have been lowered\n");
       return false;
    default:
diff --git a/src/nouveau/codegen/nv50_ir_emit_nv50.cpp b/src/nouveau/codegen/nv50_ir_emit_nv50.cpp
index 48af3d2ad62..e616801c41f 100644
--- a/src/nouveau/codegen/nv50_ir_emit_nv50.cpp
+++ b/src/nouveau/codegen/nv50_ir_emit_nv50.cpp
@@ -2131,7 +2131,6 @@ CodeEmitterNV50::emitInstruction(Instruction *insn)
    case OP_EXP:
    case OP_LOG:
    case OP_SQRT:
-   case OP_POW:
    case OP_SELP:
    case OP_SLCT:
    case OP_TXD:
diff --git a/src/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 552234e7be6..3bd8a78b965 100644
--- a/src/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -2939,7 +2939,6 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
    case OP_EXP:
    case OP_LOG:
    case OP_SQRT:
-   case OP_POW:
       ERROR("operation should have been lowered\n");
       return false;
    default:
diff --git a/src/nouveau/codegen/nv50_ir_lowering_nv50.cpp b/src/nouveau/codegen/nv50_ir_lowering_nv50.cpp
index 73e72339cac..a3e44b444a2 100644
--- a/src/nouveau/codegen/nv50_ir_lowering_nv50.cpp
+++ b/src/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -656,7 +656,6 @@ private:
 
    bool handleDIV(Instruction *);
    bool handleSQRT(Instruction *);
-   bool handlePOW(Instruction *);
 
    bool handleSET(Instruction *);
    bool handleSLCT(CmpInstruction *);
@@ -1364,22 +1363,6 @@ NV50LoweringPreSSA::handleSQRT(Instruction *i)
    return true;
 }
 
-bool
-NV50LoweringPreSSA::handlePOW(Instruction *i)
-{
-   LValue *val = bld.getScratch();
-
-   bld.mkOp1(OP_LG2, TYPE_F32, val, i->getSrc(0));
-   bld.mkOp2(OP_MUL, TYPE_F32, val, i->getSrc(1), val)->dnz = 1;
-   bld.mkOp1(OP_PREEX2, TYPE_F32, val, val);
-
-   i->op = OP_EX2;
-   i->setSrc(0, val);
-   i->setSrc(1, NULL);
-
-   return true;
-}
-
 bool
 NV50LoweringPreSSA::handleEXPORT(Instruction *i)
 {
@@ -2215,8 +2198,6 @@ NV50LoweringPreSSA::visit(Instruction *i)
       return handleSLCT(i->asCmp());
    case OP_SELP:
       return handleSELP(i);
-   case OP_POW:
-      return handlePOW(i);
    case OP_DIV:
       return handleDIV(i);
    case OP_SQRT:
diff --git a/src/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index f2190a9a654..486bb26c4b1 100644
--- a/src/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -3188,22 +3188,6 @@ NVC0LoweringPass::handleSQRT(Instruction *i)
    return true;
 }
 
-bool
-NVC0LoweringPass::handlePOW(Instruction *i)
-{
-   LValue *val = bld.getScratch();
-
-   bld.mkOp1(OP_LG2, TYPE_F32, val, i->getSrc(0));
-   bld.mkOp2(OP_MUL, TYPE_F32, val, i->getSrc(1), val)->dnz = 1;
-   bld.mkOp1(OP_PREEX2, TYPE_F32, val, val);
-
-   i->op = OP_EX2;
-   i->setSrc(0, val);
-   i->setSrc(1, NULL);
-
-   return true;
-}
-
 bool
 NVC0LoweringPass::handleEXPORT(Instruction *i)
 {
@@ -3364,8 +3348,6 @@ NVC0LoweringPass::visit(Instruction *i)
       bld.mkOp1(OP_PREEX2, TYPE_F32, i->getDef(0), i->getSrc(0));
       i->setSrc(0, i->getDef(0));
       break;
-   case OP_POW:
-      return handlePOW(i);
    case OP_DIV:
       return handleDIV(i);
    case OP_MOD:
diff --git a/src/nouveau/codegen/nv50_ir_lowering_nvc0.h b/src/nouveau/codegen/nv50_ir_lowering_nvc0.h
index 0aefa071c55..17c944aec6f 100644
--- a/src/nouveau/codegen/nv50_ir_lowering_nvc0.h
+++ b/src/nouveau/codegen/nv50_ir_lowering_nvc0.h
@@ -135,7 +135,6 @@ protected:
    bool handleDIV(Instruction *);
    bool handleMOD(Instruction *);
    bool handleSQRT(Instruction *);
-   bool handlePOW(Instruction *);
    bool handleTEX(TexInstruction *);
    bool handleTXD(TexInstruction *);
    bool handleTXQ(TexInstruction *);
diff --git a/src/nouveau/codegen/nv50_ir_peephole.cpp b/src/nouveau/codegen/nv50_ir_peephole.cpp
index 53f4b106157..419374093d6 100644
--- a/src/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/nouveau/codegen/nv50_ir_peephole.cpp
@@ -636,14 +636,6 @@ ConstantFolding::expr(Instruction *i,
          return;
       }
       break;
-   case OP_POW:
-      switch (i->dType) {
-      case TYPE_F32: res.data.f32 = pow(a->data.f32, b->data.f32); break;
-      case TYPE_F64: res.data.f64 = pow(a->data.f64, b->data.f64); break;
-      default:
-         return;
-      }
-      break;
    case OP_MAX:
       switch (i->dType) {
       case TYPE_F32: res.data.f32 = MAX2(a->data.f32, b->data.f32); break;
diff --git a/src/nouveau/codegen/nv50_ir_print.cpp b/src/nouveau/codegen/nv50_ir_print.cpp
index a86872947aa..bd7a82821e1 100644
--- a/src/nouveau/codegen/nv50_ir_print.cpp
+++ b/src/nouveau/codegen/nv50_ir_print.cpp
@@ -122,7 +122,6 @@ const char *operationStr[OP_LAST + 1] =
    "presin",
    "preex2",
    "sqrt",
-   "pow",
    "bra",
    "call",
    "ret",
diff --git a/src/nouveau/codegen/nv50_ir_target.cpp b/src/nouveau/codegen/nv50_ir_target.cpp
index f4464da7a85..c65eceb374e 100644
--- a/src/nouveau/codegen/nv50_ir_target.cpp
+++ b/src/nouveau/codegen/nv50_ir_target.cpp
@@ -38,7 +38,7 @@ const uint8_t Target::operationSrcNr[] =
    1, 1, 1, 1,             // CEIL, FLOOR, TRUNC, CVT
    3, 3, 3, 2, 3, 3,       // SET_AND,OR,XOR, SET, SELP, SLCT
    1, 1, 1, 1, 1, 1,       // RCP, RSQ, LG2, SIN, COS, EX2
-   1, 1, 1, 1, 1, 2,       // EXP, LOG, PRESIN, PREEX2, SQRT, POW
+   1, 1, 1, 1, 1,          // EXP, LOG, PRESIN, PREEX2, SQRT
    0, 0, 0, 0, 0,          // BRA, CALL, RET, CONT, BREAK,
    0, 0, 0,                // PRERET,CONT,BREAK
    0, 0, 0, 0, 0, 0,       // BRKPT, JOINAT, JOIN, DISCARD, EXIT, MEMBAR
@@ -89,10 +89,10 @@ const OpClass Target::operationClass[] =
    // SET(AND,OR,XOR); SELP, SLCT
    OPCLASS_COMPARE, OPCLASS_COMPARE, OPCLASS_COMPARE, OPCLASS_COMPARE,
    OPCLASS_COMPARE, OPCLASS_COMPARE,
-   // RCP, RSQ, LG2, SIN, COS; EX2, EXP, LOG, PRESIN, PREEX2; SQRT, POW
+   // RCP, RSQ, LG2, SIN, COS; EX2, EXP, LOG, PRESIN, PREEX2; SQRT
    OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU,
    OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU, OPCLASS_SFU,
-   OPCLASS_SFU, OPCLASS_SFU,
+   OPCLASS_SFU,
    // BRA, CALL, RET; CONT, BREAK, PRE(RET,CONT,BREAK); BRKPT, JOINAT, JOIN
    OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW,
    OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW, OPCLASS_FLOW,
diff --git a/src/nouveau/codegen/nv50_ir_target_gm107.cpp b/src/nouveau/codegen/nv50_ir_target_gm107.cpp
index 043aefcf917..b313bf06844 100644
--- a/src/nouveau/codegen/nv50_ir_target_gm107.cpp
+++ b/src/nouveau/codegen/nv50_ir_target_gm107.cpp
@@ -56,7 +56,6 @@ TargetGM107::isOpSupported(operation op, DataType ty) const
 {
    switch (op) {
    case OP_SAD:
-   case OP_POW:
    case OP_DIV:
    case OP_MOD:
       return false;
diff --git a/src/nouveau/codegen/nv50_ir_target_nv50.cpp b/src/nouveau/codegen/nv50_ir_target_nv50.cpp
index 0b086469662..4bbef49df79 100644
--- a/src/nouveau/codegen/nv50_ir_target_nv50.cpp
+++ b/src/nouveau/codegen/nv50_ir_target_nv50.cpp
@@ -439,7 +439,6 @@ TargetNV50::isOpSupported(operation op, DataType ty) const
       return chipset >= 0xa0;
    case OP_TXG:
       return chipset >= 0xa3 && chipset != 0xaa && chipset != 0xac;
-   case OP_POW:
    case OP_SQRT:
    case OP_DIV:
    case OP_MOD:
diff --git a/src/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/nouveau/codegen/nv50_ir_target_nvc0.cpp
index 475539091eb..beeac755b55 100644
--- a/src/nouveau/codegen/nv50_ir_target_nvc0.cpp
+++ b/src/nouveau/codegen/nv50_ir_target_nvc0.cpp
@@ -482,7 +482,7 @@ TargetNVC0::isOpSupported(operation op, DataType ty) const
 {
    if (op == OP_SAD && ty != TYPE_S32 && ty != TYPE_U32)
       return false;
-   if (op == OP_POW || op == OP_SQRT || op == OP_DIV || op == OP_MOD)
+   if (op == OP_SQRT || op == OP_DIV || op == OP_MOD)
       return false;
    if (op == OP_XMAD)
       return false;