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gallium: drop pipe_compute_state.req_private_mem
nothing used it and nothing will use it, so just drop it and clean up some dead struct fields in drivers. Signed-off-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18581>
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b5a3b9f555
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2a52297141
13 changed files with 4 additions and 23 deletions
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@ -350,7 +350,6 @@ void trace_dump_compute_state(const struct pipe_compute_state *state)
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trace_dump_member_end();
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trace_dump_member(uint, state, req_local_mem);
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trace_dump_member(uint, state, req_private_mem);
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trace_dump_member(uint, state, req_input_mem);
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trace_dump_struct_end();
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@ -107,7 +107,6 @@ struct nv50_program {
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} gp;
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struct {
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uint32_t lmem_size; /* local memory (TGSI PRIVATE resource) size */
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uint32_t smem_size; /* shared memory (TGSI LOCAL resource) size */
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struct nv50_gmem_state gmem[NV50_MAX_GLOBALS];
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} cp;
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@ -862,7 +862,6 @@ nv50_cp_state_create(struct pipe_context *pipe,
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}
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prog->cp.smem_size = cso->req_local_mem;
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prog->cp.lmem_size = cso->req_private_mem;
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prog->parm_size = cso->req_input_mem;
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return (void *)prog;
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@ -441,7 +441,7 @@ nvc0_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
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PUSH_DATA (push, cp->code_base);
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BEGIN_NVC0(push, NVC0_CP(LOCAL_POS_ALLOC), 3);
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PUSH_DATA (push, (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10));
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PUSH_DATA (push, cp->hdr[1] & 0xfffff0);
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PUSH_DATA (push, 0);
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PUSH_DATA (push, 0x800); /* WARP_CSTACK_SIZE */
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@ -60,7 +60,6 @@ struct nvc0_program {
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uint32_t tess_mode; /* ~0 if defined by the other stage */
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} tp;
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struct {
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uint32_t lmem_size; /* local memory (TGSI PRIVATE resource) size */
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uint32_t smem_size; /* shared memory (TGSI LOCAL resource) size */
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} cp;
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uint8_t num_barriers;
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@ -742,7 +742,6 @@ nvc0_cp_state_create(struct pipe_context *pipe,
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prog->pipe.type = cso->ir_type;
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prog->cp.smem_size = cso->req_local_mem;
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prog->cp.lmem_size = cso->req_private_mem;
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prog->parm_size = cso->req_input_mem;
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switch(cso->ir_type) {
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@ -649,9 +649,7 @@ nve4_compute_setup_launch_desc(struct nvc0_context *nvc0, uint32_t *qmd,
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NVA0C0_QMDV00_06_VAL_SET(qmd, SHARED_MEMORY_SIZE,
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align(cp->cp.smem_size, 0x100));
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NVA0C0_QMDV00_06_VAL_SET(qmd, SHADER_LOCAL_MEMORY_LOW_SIZE,
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(cp->hdr[1] & 0xfffff0) +
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align(cp->cp.lmem_size, 0x10));
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NVA0C0_QMDV00_06_VAL_SET(qmd, SHADER_LOCAL_MEMORY_LOW_SIZE, cp->hdr[1] & 0xfffff0);
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NVA0C0_QMDV00_06_VAL_SET(qmd, SHADER_LOCAL_MEMORY_HIGH_SIZE, 0);
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NVA0C0_QMDV00_06_VAL_SET(qmd, SHADER_LOCAL_MEMORY_CRS_SIZE, 0x800);
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@ -709,9 +707,7 @@ gp100_compute_setup_launch_desc(struct nvc0_context *nvc0, uint32_t *qmd,
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NVC0C0_QMDV02_01_VAL_SET(qmd, SHARED_MEMORY_SIZE,
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align(cp->cp.smem_size, 0x100));
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NVC0C0_QMDV02_01_VAL_SET(qmd, SHADER_LOCAL_MEMORY_LOW_SIZE,
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(cp->hdr[1] & 0xfffff0) +
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align(cp->cp.lmem_size, 0x10));
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NVC0C0_QMDV02_01_VAL_SET(qmd, SHADER_LOCAL_MEMORY_LOW_SIZE, cp->hdr[1] & 0xfffff0);
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NVC0C0_QMDV02_01_VAL_SET(qmd, SHADER_LOCAL_MEMORY_HIGH_SIZE, 0);
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NVC0C0_QMDV02_01_VAL_SET(qmd, SHADER_LOCAL_MEMORY_CRS_SIZE, 0x800);
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@ -759,9 +755,7 @@ gv100_compute_setup_launch_desc(struct nvc0_context *nvc0, u32 *qmd,
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NVC3C0_QMDV02_02_DEF_SET(qmd, SAMPLER_INDEX, INDEPENDENTLY);
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NVC3C0_QMDV02_02_VAL_SET(qmd, SHARED_MEMORY_SIZE,
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align(cp->cp.smem_size, 0x100));
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NVC3C0_QMDV02_02_VAL_SET(qmd, SHADER_LOCAL_MEMORY_LOW_SIZE,
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(cp->hdr[1] & 0xfffff0) +
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align(cp->cp.lmem_size, 0x10));
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NVC3C0_QMDV02_02_VAL_SET(qmd, SHADER_LOCAL_MEMORY_LOW_SIZE, cp->hdr[1] & 0xfffff0);
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NVC3C0_QMDV02_02_VAL_SET(qmd, SHADER_LOCAL_MEMORY_HIGH_SIZE, 0);
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NVC3C0_QMDV02_02_VAL_SET(qmd, MIN_SM_CONFIG_SHARED_MEM_SIZE,
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gv100_sm_config_smem_size(8 * 1024));
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@ -436,7 +436,6 @@ static void *evergreen_create_compute_state(struct pipe_context *ctx,
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shader->ctx = rctx;
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shader->local_size = cso->req_local_mem;
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shader->private_size = cso->req_private_mem;
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shader->input_size = cso->req_input_mem;
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shader->ir_type = cso->ir_type;
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@ -81,7 +81,6 @@ struct r600_pipe_compute {
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struct r600_bytecode bc;
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unsigned local_size;
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unsigned private_size;
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unsigned input_size;
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struct r600_resource *kernel_param;
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@ -49,7 +49,6 @@ struct dispatch_packet {
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uint32_t grid_size_x;
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uint32_t grid_size_y;
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uint32_t grid_size_z;
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uint32_t private_segment_size;
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uint32_t group_segment_size;
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uint64_t kernel_object;
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uint64_t kernarg_address;
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@ -245,7 +244,6 @@ static void *si_create_compute_state(struct pipe_context *ctx, const struct pipe
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program->shader.selector = &program->sel;
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program->shader.wave_size = si_determine_wave_size(sscreen, &program->shader);
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program->ir_type = cso->ir_type;
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program->private_size = cso->req_private_mem;
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program->input_size = cso->req_input_mem;
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if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
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@ -684,7 +682,6 @@ static void si_setup_user_sgprs_co_v2(struct si_context *sctx, const amd_kernel_
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dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
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dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
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dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
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dispatch.group_segment_size = util_cpu_to_le32(program->sel.info.base.shared_size);
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dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
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@ -33,7 +33,6 @@ struct si_compute {
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struct si_shader shader;
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unsigned ir_type;
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unsigned private_size;
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unsigned input_size;
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int max_global_buffers;
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@ -276,7 +276,6 @@ impl PipeContext {
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prog: nir.dup_for_driver().cast(),
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req_input_mem: input_mem,
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req_local_mem: local_mem,
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req_private_mem: 0,
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};
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unsafe { self.pipe.as_ref().create_compute_state.unwrap()(self.pipe.as_ptr(), &state) }
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}
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@ -1006,7 +1006,6 @@ struct pipe_compute_state
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enum pipe_shader_ir ir_type; /**< IR type contained in prog. */
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const void *prog; /**< Compute program to be executed. */
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unsigned req_local_mem; /**< Required size of the LOCAL resource. */
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unsigned req_private_mem; /**< Required size of the PRIVATE resource. */
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unsigned req_input_mem; /**< Required size of the INPUT resource. */
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};
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