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i965: stop passing gl_shader_program to brw_nir_setup_glsl_uniforms()

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We can now just get the data needed from the gl_shader_program_data
pointer in gl_program.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Timothy Arceri 2016-11-07 20:54:45 +11:00
parent d3b2ee6b49
commit 2a4d169735
8 changed files with 13 additions and 18 deletions
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4
src/mesa/drivers/dri/i965/brw_cs.c
View file

@ -102,8 +102,8 @@ brw_codegen_cs_prog(struct brw_context *brw,
prog_data.base.nr_params = param_count;
prog_data.base.nr_image_params = cp->program.info.num_images;
brw_nir_setup_glsl_uniforms(cp->program.nir, prog, &cp->program,
&prog_data.base, true);
brw_nir_setup_glsl_uniforms(cp->program.nir, &cp->program,&prog_data.base,
true);
if (unlikely(brw->perf_debug)) {
start_busy = (brw->batch.last_bo &&

2
src/mesa/drivers/dri/i965/brw_gs.c
View file

@ -123,7 +123,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
prog_data.base.base.nr_params = param_count;
prog_data.base.base.nr_image_params = gp->program.info.num_images;
brw_nir_setup_glsl_uniforms(gp->program.nir, prog, &gp->program,
brw_nir_setup_glsl_uniforms(gp->program.nir, &gp->program,
&prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_GEOMETRY]);

1
src/mesa/drivers/dri/i965/brw_nir.h
View file

@ -135,7 +135,6 @@ enum brw_reg_type brw_type_for_nir_type(nir_alu_type type);
enum glsl_base_type brw_glsl_base_type_for_nir_type(nir_alu_type type);
void brw_nir_setup_glsl_uniforms(nir_shader *shader,
struct gl_shader_program *shader_prog,
const struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
bool is_scalar);

14
src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
View file

@ -68,7 +68,7 @@ brw_nir_setup_glsl_builtin_uniform(nir_variable *var,
static void
brw_nir_setup_glsl_uniform(gl_shader_stage stage, nir_variable *var,
struct gl_shader_program *shader_prog,
const struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
bool is_scalar)
{
@ -81,9 +81,9 @@ brw_nir_setup_glsl_uniform(gl_shader_stage stage, nir_variable *var,
* with our name, or the prefix of a component that starts with our name.
*/
unsigned uniform_index = var->data.driver_location / 4;
for (unsigned u = 0; u < shader_prog->data->NumUniformStorage; u++) {
for (unsigned u = 0; u < prog->sh.data->NumUniformStorage; u++) {
struct gl_uniform_storage *storage =
&shader_prog->data->UniformStorage[u];
&prog->sh.data->UniformStorage[u];
if (storage->builtin)
continue;
@ -131,9 +131,7 @@ brw_nir_setup_glsl_uniform(gl_shader_stage stage, nir_variable *var,
}
void
brw_nir_setup_glsl_uniforms(nir_shader *shader,
struct gl_shader_program *shader_prog,
const struct gl_program *prog,
brw_nir_setup_glsl_uniforms(nir_shader *shader, const struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
bool is_scalar)
{
@ -147,8 +145,8 @@ brw_nir_setup_glsl_uniforms(nir_shader *shader,
brw_nir_setup_glsl_builtin_uniform(var, prog, stage_prog_data,
is_scalar);
} else {
brw_nir_setup_glsl_uniform(shader->stage, var, shader_prog,
stage_prog_data, is_scalar);
brw_nir_setup_glsl_uniform(shader->stage, var, prog, stage_prog_data,
is_scalar);
}
}
}

3
src/mesa/drivers/dri/i965/brw_tcs.c
View file

@ -218,8 +218,7 @@ brw_codegen_tcs_prog(struct brw_context *brw,
tcp->program.info.num_images);
prog_data.base.base.nr_image_params = tcp->program.info.num_images;
brw_nir_setup_glsl_uniforms(nir, shader_prog, &tcp->program,
&prog_data.base.base,
brw_nir_setup_glsl_uniforms(nir, &tcp->program, &prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
} else {
/* Upload the Patch URB Header as the first two uniforms.

3
src/mesa/drivers/dri/i965/brw_tes.c
View file

@ -160,8 +160,7 @@ brw_codegen_tes_prog(struct brw_context *brw,
prog_data.base.base.nr_params = param_count;
prog_data.base.base.nr_image_params = tep->program.info.num_images;
brw_nir_setup_glsl_uniforms(nir, shader_prog, &tep->program,
&prog_data.base.base,
brw_nir_setup_glsl_uniforms(nir, &tep->program, &prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
int st_index = -1;

2
src/mesa/drivers/dri/i965/brw_vs.c
View file

@ -187,7 +187,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
stage_prog_data->nr_params = param_count;
if (prog) {
brw_nir_setup_glsl_uniforms(vp->program.nir, prog, &vp->program,
brw_nir_setup_glsl_uniforms(vp->program.nir, &vp->program,
&prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_VERTEX]);
} else {

2
src/mesa/drivers/dri/i965/brw_wm.c
View file

@ -174,7 +174,7 @@ brw_codegen_wm_prog(struct brw_context *brw,
prog_data.base.nr_params = param_count;
if (prog) {
brw_nir_setup_glsl_uniforms(fp->program.nir, prog, &fp->program,
brw_nir_setup_glsl_uniforms(fp->program.nir, &fp->program,
&prog_data.base, true);
} else {
brw_nir_setup_arb_uniforms(fp->program.nir, &fp->program,