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nvc0/ir: Allow 0/1 immediate value as source of OP_VOTE
Implementation of readFirstInvocationARB() on nvidia hardware needs a ballotARB(true) used to decide the first active thread. This expressed in gm107 asm as (supposing output is $r0): vote any $r0 0x1 0x1 To model the always true input, which corresponds to the second 0x1 above, we make OP_VOTE accept immediate value 0/1 and emit "0x1" and "not 0x1" in the src field respectively. v2: Make sure that asImm() is not NULL (Samuel Pitoiset) v3: (Ilia Mirkin) Make the handling more symmetric with predicate version in gm107 Use i->getSrc(s) Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
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3 changed files with 60 additions and 11 deletions
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@ -1621,7 +1621,8 @@ CodeEmitterGK110::emitSHFL(const Instruction *i)
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void
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CodeEmitterGK110::emitVOTE(const Instruction *i)
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{
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assert(i->src(0).getFile() == FILE_PREDICATE);
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const ImmediateValue *imm;
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uint32_t u32;
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code[0] = 0x00000002;
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code[1] = 0x86c00000 | (i->subOp << 19);
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@ -1646,9 +1647,24 @@ CodeEmitterGK110::emitVOTE(const Instruction *i)
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code[0] |= 255 << 2;
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if (!(rp & 2))
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code[1] |= 7 << 16;
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if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
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code[1] |= 1 << 13;
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srcId(i->src(0), 42);
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switch (i->src(0).getFile()) {
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case FILE_PREDICATE:
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if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
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code[0] |= 1 << 13;
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srcId(i->src(0), 42);
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break;
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case FILE_IMMEDIATE:
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imm = i->getSrc(0)->asImm();
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assert(imm);
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u32 = imm->reg.data.u32;
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assert(u32 == 0 || u32 == 1);
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code[1] |= (u32 == 1 ? 0x7 : 0xf) << 10;
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break;
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default:
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assert(!"Unhandled src");
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break;
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}
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}
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void
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@ -2931,7 +2931,8 @@ CodeEmitterGM107::emitMEMBAR()
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void
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CodeEmitterGM107::emitVOTE()
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{
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assert(insn->src(0).getFile() == FILE_PREDICATE);
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const ImmediateValue *imm;
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uint32_t u32;
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int r = -1, p = -1;
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for (int i = 0; insn->defExists(i); i++) {
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@ -2951,8 +2952,24 @@ CodeEmitterGM107::emitVOTE()
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emitPRED (0x2d, insn->def(p));
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else
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emitPRED (0x2d);
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emitField(0x2a, 1, insn->src(0).mod == Modifier(NV50_IR_MOD_NOT));
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emitPRED (0x27, insn->src(0));
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switch (insn->src(0).getFile()) {
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case FILE_PREDICATE:
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emitField(0x2a, 1, insn->src(0).mod == Modifier(NV50_IR_MOD_NOT));
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emitPRED (0x27, insn->src(0));
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break;
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case FILE_IMMEDIATE:
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imm = insn->getSrc(0)->asImm();
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assert(imm);
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u32 = imm->reg.data.u32;
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assert(u32 == 0 || u32 == 1);
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emitPRED(0x27);
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emitField(0x2a, 1, u32 == 0);
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break;
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default:
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assert(!"Unhandled src");
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break;
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}
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}
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void
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@ -2583,7 +2583,8 @@ CodeEmitterNVC0::emitSHFL(const Instruction *i)
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void
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CodeEmitterNVC0::emitVOTE(const Instruction *i)
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{
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assert(i->src(0).getFile() == FILE_PREDICATE);
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const ImmediateValue *imm;
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uint32_t u32;
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code[0] = 0x00000004 | (i->subOp << 5);
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code[1] = 0x48000000;
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@ -2608,9 +2609,24 @@ CodeEmitterNVC0::emitVOTE(const Instruction *i)
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code[0] |= 63 << 14;
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if (!(rp & 2))
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code[1] |= 7 << 22;
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if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
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code[0] |= 1 << 23;
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srcId(i->src(0), 20);
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switch (i->src(0).getFile()) {
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case FILE_PREDICATE:
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if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
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code[0] |= 1 << 23;
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srcId(i->src(0), 20);
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break;
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case FILE_IMMEDIATE:
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imm = i->getSrc(0)->asImm();
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assert(imm);
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u32 = imm->reg.data.u32;
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assert(u32 == 0 || u32 == 1);
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code[0] |= (u32 == 1 ? 0x7 : 0xf) << 20;
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break;
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default:
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assert(!"Unhandled src");
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break;
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}
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}
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bool
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