From 29ecb7acf18228f34ffda45976529841d044a672 Mon Sep 17 00:00:00 2001
From: Faith Ekstrand <faith.ekstrand@collabora.com>
Date: Mon, 10 Apr 2023 17:23:24 -0500
Subject: [PATCH] nak: Rename Imm to Imm32

It's always 32-bit as far as I can tell.  We'll do something else for
booleans.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24998>
---
 src/nouveau/compiler/nak_encode_sm75.rs | 14 +++++++-------
 src/nouveau/compiler/nak_ir.rs          | 19 +++++++------------
 src/nouveau/compiler/nak_legalize.rs    |  2 +-
 3 files changed, 15 insertions(+), 20 deletions(-)

diff --git a/src/nouveau/compiler/nak_encode_sm75.rs b/src/nouveau/compiler/nak_encode_sm75.rs
index 2d9c10460eb..825b6da47cd 100644
--- a/src/nouveau/compiler/nak_encode_sm75.rs
+++ b/src/nouveau/compiler/nak_encode_sm75.rs
@@ -23,7 +23,7 @@ struct ALUCBufRef {
 
 enum ALUSrc {
     None,
-    Imm(Immediate),
+    Imm32(u32),
     Reg(ALURegRef),
     UReg(ALURegRef),
     CBuf(ALUCBufRef),
@@ -45,9 +45,9 @@ impl ALUSrc {
                     _ => panic!("Invalid ALU register file"),
                 }
             }
-            SrcRef::Imm(i) => {
+            SrcRef::Imm32(i) => {
                 assert!(src.src_mod.is_none());
-                ALUSrc::Imm(i)
+                ALUSrc::Imm32(i)
             }
             SrcRef::CBuf(cb) => {
                 let alu_ref = ALUCBufRef {
@@ -112,9 +112,9 @@ impl BitSetMutViewable for SM75Instr {
 impl BitSetMut for SM75Instr {}
 
 impl SM75Instr {
-    fn set_src_imm(&mut self, range: Range<usize>, imm: &Immediate) {
+    fn set_src_imm(&mut self, range: Range<usize>, u: &u32) {
         assert!(range.len() == 32);
-        self.set_field(range, imm.u);
+        self.set_field(range, *u);
     }
 
     fn set_reg(&mut self, range: Range<usize>, reg: RegRef) {
@@ -297,7 +297,7 @@ impl SM75Instr {
                         self.set_alu_reg(64..72, 74, 75, reg1);
                         7_u8 /* form */
                     }
-                    ALUSrc::Imm(imm) => {
+                    ALUSrc::Imm32(imm) => {
                         self.set_src_imm(32..64, &imm);
                         self.set_alu_reg(64..72, 74, 75, reg1);
                         2_u8 /* form */
@@ -315,7 +315,7 @@ impl SM75Instr {
                 self.set_alu_reg_src(64..72, 74, 75, &src2);
                 6_u8 /* form */
             }
-            ALUSrc::Imm(imm) => {
+            ALUSrc::Imm32(imm) => {
                 self.set_src_imm(32..64, &imm);
                 self.set_alu_reg_src(64..72, 74, 75, &src2);
                 4_u8 /* form */
diff --git a/src/nouveau/compiler/nak_ir.rs b/src/nouveau/compiler/nak_ir.rs
index 150b9ac529a..4381e8ac595 100644
--- a/src/nouveau/compiler/nak_ir.rs
+++ b/src/nouveau/compiler/nak_ir.rs
@@ -9,11 +9,6 @@ use nak_ir_proc::*;
 use std::fmt;
 use std::ops::{BitAnd, BitOr, Not, Range};
 
-#[derive(Clone, Copy)]
-pub struct Immediate {
-    pub u: u32,
-}
-
 #[repr(u8)]
 #[derive(Clone, Copy, Eq, Hash, PartialEq)]
 pub enum RegFile {
@@ -282,7 +277,7 @@ pub struct CBufRef {
 #[derive(Clone, Copy)]
 pub enum SrcRef {
     Zero,
-    Imm(Immediate),
+    Imm32(u32),
     CBuf(CBufRef),
     SSA(SSAValue),
     Reg(RegRef),
@@ -305,7 +300,7 @@ impl SrcRef {
 
     pub fn get_reg(&self) -> Option<&RegRef> {
         match self {
-            SrcRef::Zero | SrcRef::Imm(_) | SrcRef::SSA(_) => None,
+            SrcRef::Zero | SrcRef::Imm32(_) | SrcRef::SSA(_) => None,
             SrcRef::CBuf(cb) => match &cb.buf {
                 CBuf::Binding(_) | CBuf::BindlessSSA(_) => None,
                 CBuf::BindlessGPR(reg) => Some(reg),
@@ -316,7 +311,7 @@ impl SrcRef {
 
     pub fn get_ssa(&self) -> Option<&SSAValue> {
         match self {
-            SrcRef::Zero | SrcRef::Imm(_) | SrcRef::Reg(_) => None,
+            SrcRef::Zero | SrcRef::Imm32(_) | SrcRef::Reg(_) => None,
             SrcRef::CBuf(cb) => match &cb.buf {
                 CBuf::Binding(_) | CBuf::BindlessGPR(_) => None,
                 CBuf::BindlessSSA(ssa) => Some(ssa),
@@ -342,7 +337,7 @@ impl fmt::Display for SrcRef {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         match self {
             SrcRef::Zero => write!(f, "ZERO")?,
-            SrcRef::Imm(x) => write!(f, "{:#x}", x.u)?,
+            SrcRef::Imm32(u) => write!(f, "{:#x}", u)?,
             SrcRef::CBuf(r) => {
                 match r.buf {
                     CBuf::Binding(idx) => write!(f, "c[{:#x}]", idx)?,
@@ -453,7 +448,7 @@ impl Src {
     }
 
     pub fn new_imm_u32(u: u32) -> Src {
-        SrcRef::Imm(Immediate { u: u }).into()
+        SrcRef::Imm32(u).into()
     }
 
     pub fn new_cbuf(idx: u8, offset: u16) -> Src {
@@ -503,7 +498,7 @@ impl Src {
 
     pub fn is_uniform(&self) -> bool {
         match self.src_ref {
-            SrcRef::Zero | SrcRef::Imm(_) | SrcRef::CBuf(_) => true,
+            SrcRef::Zero | SrcRef::Imm32(_) | SrcRef::CBuf(_) => true,
             SrcRef::SSA(ssa) => ssa.is_uniform(),
             SrcRef::Reg(reg) => reg.is_uniform(),
         }
@@ -519,7 +514,7 @@ impl Src {
     pub fn is_reg_or_zero(&self) -> bool {
         match self.src_ref {
             SrcRef::Zero | SrcRef::SSA(_) | SrcRef::Reg(_) => true,
-            SrcRef::Imm(_) | SrcRef::CBuf(_) => false,
+            SrcRef::Imm32(_) | SrcRef::CBuf(_) => false,
         }
     }
 }
diff --git a/src/nouveau/compiler/nak_legalize.rs b/src/nouveau/compiler/nak_legalize.rs
index 5de80c7b2ea..054ef696e21 100644
--- a/src/nouveau/compiler/nak_legalize.rs
+++ b/src/nouveau/compiler/nak_legalize.rs
@@ -13,7 +13,7 @@ struct LegalizeInstr<'a> {
 fn src_is_reg(src: &Src) -> bool {
     match src.src_ref {
         SrcRef::Zero | SrcRef::SSA(_) => true,
-        SrcRef::Imm(_) | SrcRef::CBuf(_) => false,
+        SrcRef::Imm32(_) | SrcRef::CBuf(_) => false,
         SrcRef::Reg(_) => panic!("Not in SSA form"),
     }
 }