mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-21 09:20:12 +01:00
i965/fs: Remove extract virtual opcodes.
These can be easily represented in the IR as a MOV instruction with strided source so they seem rather redundant. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
parent
9dcb8ff6a1
commit
29ce110be6
5 changed files with 9 additions and 53 deletions
|
|
@ -1086,18 +1086,6 @@ enum opcode {
|
|||
*/
|
||||
SHADER_OPCODE_BROADCAST,
|
||||
|
||||
/**
|
||||
* Pick the byte from its first source register given by the index
|
||||
* specified as second source.
|
||||
*/
|
||||
SHADER_OPCODE_EXTRACT_BYTE,
|
||||
|
||||
/**
|
||||
* Pick the word from its first source register given by the index
|
||||
* specified as second source.
|
||||
*/
|
||||
SHADER_OPCODE_EXTRACT_WORD,
|
||||
|
||||
VEC4_OPCODE_MOV_BYTES,
|
||||
VEC4_OPCODE_PACK_BYTES,
|
||||
VEC4_OPCODE_UNPACK_UNIFORM,
|
||||
|
|
|
|||
|
|
@ -78,8 +78,6 @@ is_expression(const fs_visitor *v, const fs_inst *const inst)
|
|||
case FS_OPCODE_LINTERP:
|
||||
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
|
||||
case SHADER_OPCODE_BROADCAST:
|
||||
case SHADER_OPCODE_EXTRACT_BYTE:
|
||||
case SHADER_OPCODE_EXTRACT_WORD:
|
||||
case SHADER_OPCODE_MOV_INDIRECT:
|
||||
case FS_OPCODE_PACK:
|
||||
return true;
|
||||
|
|
|
|||
|
|
@ -2050,28 +2050,6 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
|
|||
brw_broadcast(p, dst, src[0], src[1]);
|
||||
break;
|
||||
|
||||
case SHADER_OPCODE_EXTRACT_BYTE: {
|
||||
assert(src[0].type == BRW_REGISTER_TYPE_D ||
|
||||
src[0].type == BRW_REGISTER_TYPE_UD);
|
||||
|
||||
enum brw_reg_type type =
|
||||
src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_B
|
||||
: BRW_REGISTER_TYPE_UB;
|
||||
brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 4));
|
||||
break;
|
||||
}
|
||||
|
||||
case SHADER_OPCODE_EXTRACT_WORD: {
|
||||
assert(src[0].type == BRW_REGISTER_TYPE_D ||
|
||||
src[0].type == BRW_REGISTER_TYPE_UD);
|
||||
|
||||
enum brw_reg_type type =
|
||||
src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_W
|
||||
: BRW_REGISTER_TYPE_UW;
|
||||
brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 2));
|
||||
break;
|
||||
}
|
||||
|
||||
case FS_OPCODE_SET_SAMPLE_ID:
|
||||
generate_set_sample_id(inst, dst, src[0], src[1]);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -529,14 +529,10 @@ fs_visitor::optimize_extract_to_float(nir_alu_instr *instr,
|
|||
nir_const_value *element = nir_src_as_const_value(src0->src[1].src);
|
||||
assert(element != NULL);
|
||||
|
||||
enum opcode extract_op;
|
||||
if (src0->op == nir_op_extract_u16 || src0->op == nir_op_extract_i16) {
|
||||
assert(element->u32[0] <= 1);
|
||||
extract_op = SHADER_OPCODE_EXTRACT_WORD;
|
||||
} else {
|
||||
assert(element->u32[0] <= 3);
|
||||
extract_op = SHADER_OPCODE_EXTRACT_BYTE;
|
||||
}
|
||||
/* Element type to extract.*/
|
||||
const brw_reg_type type = brw_int_type(
|
||||
src0->op == nir_op_extract_u16 || src0->op == nir_op_extract_i16 ? 2 : 1,
|
||||
src0->op == nir_op_extract_i16 || src0->op == nir_op_extract_i8);
|
||||
|
||||
fs_reg op0 = get_nir_src(src0->src[0].src);
|
||||
op0.type = brw_type_for_nir_type(
|
||||
|
|
@ -545,7 +541,7 @@ fs_visitor::optimize_extract_to_float(nir_alu_instr *instr,
|
|||
op0 = offset(op0, bld, src0->src[0].swizzle[0]);
|
||||
|
||||
set_saturate(instr->dest.saturate,
|
||||
bld.emit(extract_op, result, op0, brw_imm_ud(element->u32[0])));
|
||||
bld.MOV(result, subscript(op0, type, element->u32[0])));
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -1378,19 +1374,19 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
|
|||
|
||||
case nir_op_extract_u8:
|
||||
case nir_op_extract_i8: {
|
||||
const brw_reg_type type = brw_int_type(1, instr->op == nir_op_extract_i8);
|
||||
nir_const_value *byte = nir_src_as_const_value(instr->src[1].src);
|
||||
assert(byte != NULL);
|
||||
bld.emit(SHADER_OPCODE_EXTRACT_BYTE,
|
||||
result, op[0], brw_imm_ud(byte->u32[0]));
|
||||
bld.MOV(result, subscript(op[0], type, byte->u32[0]));
|
||||
break;
|
||||
}
|
||||
|
||||
case nir_op_extract_u16:
|
||||
case nir_op_extract_i16: {
|
||||
const brw_reg_type type = brw_int_type(2, instr->op == nir_op_extract_i16);
|
||||
nir_const_value *word = nir_src_as_const_value(instr->src[1].src);
|
||||
assert(word != NULL);
|
||||
bld.emit(SHADER_OPCODE_EXTRACT_WORD,
|
||||
result, op[0], brw_imm_ud(word->u32[0]));
|
||||
bld.MOV(result, subscript(op[0], type, word->u32[0]));
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -309,10 +309,6 @@ brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
|
|||
case SHADER_OPCODE_BROADCAST:
|
||||
return "broadcast";
|
||||
|
||||
case SHADER_OPCODE_EXTRACT_BYTE:
|
||||
return "extract_byte";
|
||||
case SHADER_OPCODE_EXTRACT_WORD:
|
||||
return "extract_word";
|
||||
case VEC4_OPCODE_MOV_BYTES:
|
||||
return "mov_bytes";
|
||||
case VEC4_OPCODE_PACK_BYTES:
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue