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anv: revert cache flushing changes for indirect commands

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This reverts commit d699600da1.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10600
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27591>
This commit is contained in:
Tapani Pälli 2024-02-13 10:24:50 +02:00 • committed by Marge Bot
parent 0c05bdf1c1
commit 29a6beb36e
1 changed files with 3 additions and 8 deletions
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11
src/intel/vulkan/genX_cmd_buffer.c
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@ -3103,16 +3103,11 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_cmd_buffer *cmd_buffer,
* UBO from the buffer, so we need to invalidate constant cache.
*/
pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
/* Indirect commands are sometimes implemented with the command
* streamer. On Gfx12.5+ we know experimentally that the command
* streamer is coherent with L3. Because that's not the case on
* previous generations we need to flush the data & tile caches.
*/
#if GFX_VERx10 < 125
pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
/* Tile cache flush needed For CmdDipatchIndirect since command
* streamer and vertex fetch aren't L3 coherent.
*/
pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
#endif
break;
case VK_ACCESS_2_INDEX_READ_BIT:
case VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT: