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radeonsi: don't flush HTILE if there is no HTILE clear

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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
This commit is contained in:
Marek Olšák 2018-03-27 21:19:15 -04:00
parent 5fb31a1734
commit 29a09e1d38
1 changed files with 2 additions and 2 deletions
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4
src/gallium/drivers/radeonsi/si_clear.c
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@ -593,9 +593,9 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
*
* This hack decreases back-to-back ClearDepth performance.
*/
if (sctx->screen->clear_db_cache_before_clear) {
if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
sctx->screen->clear_db_cache_before_clear)
sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
}
}
si_blitter_begin(sctx, SI_CLEAR);