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radv: remove redundant radeon_set_perfctr_reg() helper

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It's exactly the same as radeon_set_uconfig_reg_perfctr().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29192>
This commit is contained in:
Samuel Pitoiset 2024-05-13 16:43:22 +02:00 • committed by Marge Bot
parent 6b023780ad
commit 2957cedad7
4 changed files with 20 additions and 29 deletions
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4
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -12858,8 +12858,8 @@ radv_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstC
radeon_emit(cs, 0);
} else {
/* The PKT3 CAM bit workaround seems needed for initializing this GDS register to zero. */
radeon_set_perfctr_reg(pdev->info.gfx_level, cmd_buffer->qf, cs,
R_031088_GDS_STRMOUT_DWORDS_WRITTEN_0 + i * 4, 0);
radeon_set_uconfig_reg_perfctr(pdev->info.gfx_level, cmd_buffer->qf, cs,
R_031088_GDS_STRMOUT_DWORDS_WRITTEN_0 + i * 4, 0);
}
} else {
/* AMD GCN binds streamout buffers as shader resources.

22
src/amd/vulkan/radv_cs.h
View file

@ -112,6 +112,11 @@ static inline void
radeon_set_uconfig_reg_seq_perfctr(enum amd_gfx_level gfx_level, enum radv_queue_family qf, struct radeon_cmdbuf *cs,
unsigned reg, unsigned num)
{
/*
* On GFX10, there is a bug with the ME implementation of its content addressable memory (CAM),
* that means that it can skip register writes due to not taking correctly into account the
* fields from the GRBM_GFX_INDEX. With this bit we can force the write.
*/
const bool filter_cam_workaround = gfx_level >= GFX10 && qf == RADV_QUEUE_GENERAL;
assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
@ -148,23 +153,6 @@ radeon_set_uconfig_reg_idx(const struct radeon_info *info, struct radeon_cmdbuf
radeon_emit(cs, value);
}
static inline void
radeon_set_perfctr_reg(enum amd_gfx_level gfx_level, enum radv_queue_family qf, struct radeon_cmdbuf *cs, unsigned reg,
unsigned value)
{
assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
/*
* On GFX10, there is a bug with the ME implementation of its content addressable memory (CAM),
* that means that it can skip register writes due to not taking correctly into account the
* fields from the GRBM_GFX_INDEX. With this bit we can force the write.
*/
bool filter_cam_workaround = gfx_level >= GFX10 && qf == RADV_QUEUE_GENERAL;
radeon_set_reg_seq(cs, reg, 1, 0, CIK_UCONFIG_REG_OFFSET, PKT3_SET_UCONFIG_REG, filter_cam_workaround);
radeon_emit(cs, value);
}
static inline void
radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
{

3
src/amd/vulkan/radv_perfcounter.c
View file

@ -470,7 +470,8 @@ radv_emit_select(struct radv_cmd_buffer *cmd_buffer, struct ac_pc_block *block,
return;
for (idx = 0; idx < count; ++idx) {
radeon_set_perfctr_reg(gfx_level, qf, cs, regs->select0[idx], G_REG_SEL(selectors[idx]) | regs->select_or);
radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, regs->select0[idx],
G_REG_SEL(selectors[idx]) | regs->select_or);
}
for (idx = 0; idx < regs->num_spm_counters; idx++) {

20
src/amd/vulkan/radv_sqtt.c
View file

@ -114,14 +114,14 @@ radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs,
if (pdev->info.gfx_level >= GFX11) {
/* Order seems important for the following 2 registers. */
radeon_set_perfctr_reg(gfx_level, qf, cs, R_0367A4_SQ_THREAD_TRACE_BUF0_SIZE,
S_0367A4_SIZE(shifted_size) | S_0367A4_BASE_HI(shifted_va >> 32));
radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, R_0367A4_SQ_THREAD_TRACE_BUF0_SIZE,
S_0367A4_SIZE(shifted_size) | S_0367A4_BASE_HI(shifted_va >> 32));
radeon_set_perfctr_reg(gfx_level, qf, cs, R_0367A0_SQ_THREAD_TRACE_BUF0_BASE, shifted_va);
radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, R_0367A0_SQ_THREAD_TRACE_BUF0_BASE, shifted_va);
radeon_set_perfctr_reg(gfx_level, qf, cs, R_0367B4_SQ_THREAD_TRACE_MASK,
S_0367B4_WTYPE_INCLUDE(shader_mask) | S_0367B4_SA_SEL(0) |
S_0367B4_WGP_SEL(active_cu / 2) | S_0367B4_SIMD_SEL(0));
radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, R_0367B4_SQ_THREAD_TRACE_MASK,
S_0367B4_WTYPE_INCLUDE(shader_mask) | S_0367B4_SA_SEL(0) |
S_0367B4_WGP_SEL(active_cu / 2) | S_0367B4_SIMD_SEL(0));
uint32_t sqtt_token_mask = S_0367B8_REG_INCLUDE(V_0367B8_REG_INCLUDE_SQDEC | V_0367B8_REG_INCLUDE_SHDEC |
V_0367B8_REG_INCLUDE_GFXUDEC | V_0367B8_REG_INCLUDE_COMP |
@ -138,10 +138,11 @@ radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs,
}
sqtt_token_mask |= S_0367B8_TOKEN_EXCLUDE_GFX11(token_exclude) | S_0367B8_BOP_EVENTS_TOKEN_INCLUDE_GFX11(1);
radeon_set_perfctr_reg(gfx_level, qf, cs, R_0367B8_SQ_THREAD_TRACE_TOKEN_MASK, sqtt_token_mask);
radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, R_0367B8_SQ_THREAD_TRACE_TOKEN_MASK, sqtt_token_mask);
/* Should be emitted last (it enables thread traces). */
radeon_set_perfctr_reg(gfx_level, qf, cs, R_0367B0_SQ_THREAD_TRACE_CTRL, gfx11_get_sqtt_ctrl(device, true));
radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, R_0367B0_SQ_THREAD_TRACE_CTRL,
gfx11_get_sqtt_ctrl(device, true));
} else if (pdev->info.gfx_level >= GFX10) {
/* Order seems important for the following 2 registers. */
@ -363,7 +364,8 @@ radv_emit_sqtt_stop(const struct radv_device *device, struct radeon_cmdbuf *cs,
radeon_emit(cs, 4); /* poll interval */
/* Disable the thread trace mode. */
radeon_set_perfctr_reg(gfx_level, qf, cs, R_0367B0_SQ_THREAD_TRACE_CTRL, gfx11_get_sqtt_ctrl(device, false));
radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, R_0367B0_SQ_THREAD_TRACE_CTRL,
gfx11_get_sqtt_ctrl(device, false));
/* Wait for thread trace completion. */
radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));