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intel/fs: fix residency handling on Xe2

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We're missing a few reg_unit() scaling when dealing with residency data.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26208>
This commit is contained in:
Lionel Landwerlin 2023-11-15 17:02:18 +02:00 • committed by Marge Bot
parent 0bd23d6263
commit 295734bf88
3 changed files with 9 additions and 6 deletions
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9
src/intel/compiler/brw_fs.cpp
View file

@ -5626,6 +5626,8 @@ emit_zip(const fs_builder &lbld_before, const fs_builder &lbld_after,
assert(lbld_before.group() == lbld_after.group());
assert(lbld_after.group() >= inst->group);
const struct intel_device_info *devinfo = lbld_before.shader->devinfo;
/* Specified channel group from the destination region. */
const fs_reg dst = horiz_offset(inst->dst, lbld_after.group() - inst->group);
@ -5637,7 +5639,8 @@ emit_zip(const fs_builder &lbld_before, const fs_builder &lbld_after,
}
/* Deal with the residency data part later */
const unsigned residency_size = inst->has_sampler_residency() ? REG_SIZE : 0;
const unsigned residency_size = inst->has_sampler_residency() ?
(reg_unit(devinfo) * REG_SIZE) : 0;
const unsigned dst_size = (inst->size_written - residency_size) /
inst->dst.component_size(inst->exec_size);
@ -5715,8 +5718,8 @@ fs_visitor::lower_simd_width()
* original or the lowered instruction, whichever is lower.
*/
const unsigned n = DIV_ROUND_UP(inst->exec_size, lower_width);
const unsigned residency_size =
inst->has_sampler_residency() ? REG_SIZE : 0;
const unsigned residency_size = inst->has_sampler_residency() ?
(reg_unit(devinfo) * REG_SIZE) : 0;
const unsigned dst_size =
(inst->size_written - residency_size) /
inst->dst.component_size(inst->exec_size);

4
src/intel/compiler/brw_fs_nir.cpp
View file

@ -6702,14 +6702,14 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
if (instr->is_sparse) {
inst->size_written = (util_last_bit(write_mask) - 1) *
inst->dst.component_size(inst->exec_size) +
REG_SIZE;
(reg_unit(devinfo) * REG_SIZE);
} else {
inst->size_written = util_last_bit(write_mask) *
inst->dst.component_size(inst->exec_size);
}
} else {
inst->size_written = 4 * inst->dst.component_size(inst->exec_size) +
(instr->is_sparse ? REG_SIZE : 0);
(instr->is_sparse ? (reg_unit(devinfo) * REG_SIZE) : 0);
}
if (srcs[TEX_LOGICAL_SRC_SHADOW_C].file != BAD_FILE)

2
src/intel/compiler/brw_lower_logical_sends.cpp
View file

@ -995,7 +995,7 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op,
* and we have an explicit header, we need to set up the sampler
* writemask. It's reversed from normal: 1 means "don't write".
*/
unsigned reg_count = regs_written(inst) - residency;
unsigned reg_count = regs_written(inst) - reg_unit(devinfo) * residency;
if (!inst->eot && reg_count < 4 * reg_width) {
assert(reg_count % reg_width == 0);
unsigned mask = ~((1 << (reg_count / reg_width)) - 1) & 0xf;