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brw/compact: Precompact using 2src fields on 3src instructions

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In shader-db, with `-p skl`, shaders/0ad/12.shader_test does not
compact an instruction because precompact overwrites portions of the
instruction. (Treating the three source instruction as a two source
when accessing instruction fields.)

This instruction could be compacted:

mad(8)          g65<1>F         g61<4,4,1>F     g64<4,4,1>F     -g17<4,4,1>F { align16 1Q };

But, since precompact erroneously sets bits, the instruction isn't
compacted.

Fossil testing:

 * Tested with 0a3f3fd193 ("brw: drop unused color_outputs_valid
   key") reverted, as fossils are currently producing inconsitent
   results otherwise.

 * Tested skl, icl, dg2, mtl, lnl, bmg and ptl. Only skl had a change.

SKL:

Totals:
CodeSize: 8335219296 -> 8320248992 (-0.18%)

Totals from 359508 (14.42% of 2492689) affected shaders:
CodeSize: 2838254352 -> 2823284048 (-0.53%)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41588>
This commit is contained in:
Jordan Justen 2026-04-08 23:39:00 -07:00
parent 65b75137b4
commit 28f6a442c6
1 changed files with 3 additions and 0 deletions
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3
src/intel/compiler/brw/brw_eu_compact.c
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@ -1571,6 +1571,9 @@ has_immediate(const struct intel_device_info *devinfo, const brw_eu_inst *inst,
static brw_eu_inst
precompact(const struct brw_isa_info *isa, brw_eu_inst inst)
{
if (is_3src(isa, brw_eu_inst_opcode(isa, &inst)))
return inst;
const struct intel_device_info *devinfo = isa->devinfo;
/* In XeHP the compaction tables removed the entries for source regions