From 28e0c63a4cb209d67077b38393e82b977ad3efde Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20=C5=9Alusarz?= Date: Mon, 12 Jul 2021 13:20:22 +0200 Subject: [PATCH] intel/compiler: extract brw_nir_load_global_const out of rt code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marcin Ślusarz Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_nir.c | 46 +++++++++++++++++++ src/intel/compiler/brw_nir.h | 5 ++ .../compiler/brw_nir_lower_rt_intrinsics.c | 43 ++--------------- 3 files changed, 54 insertions(+), 40 deletions(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 262a00793e5..16a2e7ce999 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -1535,3 +1535,49 @@ brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compile return nir; } + +nir_ssa_def * +brw_nir_load_global_const(nir_builder *b, nir_intrinsic_instr *load_uniform, + nir_ssa_def *base_addr, unsigned off) +{ + assert(load_uniform->intrinsic == nir_intrinsic_load_uniform); + assert(load_uniform->dest.is_ssa); + assert(load_uniform->src[0].is_ssa); + + unsigned bit_size = load_uniform->dest.ssa.bit_size; + assert(bit_size >= 8 && bit_size % 8 == 0); + unsigned byte_size = bit_size / 8; + nir_ssa_def *sysval; + + if (nir_src_is_const(load_uniform->src[0])) { + uint64_t offset = off + + nir_intrinsic_base(load_uniform) + + nir_src_as_uint(load_uniform->src[0]); + + /* Things should be component-aligned. */ + assert(offset % byte_size == 0); + + unsigned suboffset = offset % 64; + uint64_t aligned_offset = offset - suboffset; + + /* Load two just in case we go over a 64B boundary */ + nir_ssa_def *data[2]; + for (unsigned i = 0; i < 2; i++) { + nir_ssa_def *addr = nir_iadd_imm(b, base_addr, aligned_offset + i * 64); + data[i] = nir_load_global_const_block_intel(b, 16, addr, + nir_imm_true(b)); + } + + sysval = nir_extract_bits(b, data, 2, suboffset * 8, + load_uniform->num_components, bit_size); + } else { + nir_ssa_def *offset32 = + nir_iadd_imm(b, load_uniform->src[0].ssa, + off + nir_intrinsic_base(load_uniform)); + nir_ssa_def *addr = nir_iadd(b, base_addr, nir_u2u64(b, offset32)); + sysval = nir_load_global_constant(b, addr, byte_size, + load_uniform->num_components, bit_size); + } + + return sysval; +} diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h index e95da4ac2ea..f22d39806e0 100644 --- a/src/intel/compiler/brw_nir.h +++ b/src/intel/compiler/brw_nir.h @@ -27,6 +27,7 @@ #include "brw_reg.h" #include "compiler/nir/nir.h" #include "brw_compiler.h" +#include "nir_builder.h" #ifdef __cplusplus extern "C" { @@ -191,6 +192,10 @@ nir_shader *brw_nir_create_passthrough_tcs(void *mem_ctx, bool brw_nir_move_interpolation_to_top(nir_shader *nir); bool brw_nir_demote_sample_qualifiers(nir_shader *nir); +nir_ssa_def *brw_nir_load_global_const(nir_builder *b, + nir_intrinsic_instr *load_uniform, + nir_ssa_def *base_addr, + unsigned off); #ifdef __cplusplus } diff --git a/src/intel/compiler/brw_nir_lower_rt_intrinsics.c b/src/intel/compiler/brw_nir_lower_rt_intrinsics.c index 33359a5028c..131f03d2be9 100644 --- a/src/intel/compiler/brw_nir_lower_rt_intrinsics.c +++ b/src/intel/compiler/brw_nir_lower_rt_intrinsics.c @@ -140,47 +140,10 @@ lower_rt_intrinsics_impl(nir_function_impl *impl, if (stage == MESA_SHADER_COMPUTE) break; - assert(intrin->dest.is_ssa); - assert(intrin->src[0].is_ssa); + sysval = brw_nir_load_global_const(b, intrin, + nir_load_btd_global_arg_addr_intel(b), + BRW_RT_PUSH_CONST_OFFSET); - unsigned bit_size = intrin->dest.ssa.bit_size; - assert(bit_size >= 8 && bit_size % 8 == 0); - unsigned byte_size = bit_size / 8; - - if (nir_src_is_const(intrin->src[0])) { - uint64_t offset = BRW_RT_PUSH_CONST_OFFSET + - nir_intrinsic_base(intrin) + - nir_src_as_uint(intrin->src[0]); - - /* Things should be component-aligned. */ - assert(offset % byte_size == 0); - - unsigned suboffset = offset % 64; - uint64_t aligned_offset = offset - suboffset; - - /* Load two just in case we go over a 64B boundary */ - nir_ssa_def *data[2]; - for (unsigned i = 0; i < 2; i++) { - nir_ssa_def *addr = - nir_iadd_imm(b, nir_load_btd_global_arg_addr_intel(b), - aligned_offset + i * 64); - data[i] = nir_load_global_const_block_intel(b, 16, addr, - nir_imm_true(b)); - } - - sysval = nir_extract_bits(b, data, 2, suboffset * 8, - intrin->num_components, bit_size); - } else { - nir_ssa_def *offset32 = - nir_iadd_imm(b, intrin->src[0].ssa, - BRW_RT_PUSH_CONST_OFFSET + - nir_intrinsic_base(intrin)); - nir_ssa_def *addr = - nir_iadd(b, nir_load_btd_global_arg_addr_intel(b), - nir_u2u64(b, offset32)); - sysval = nir_load_global_constant(b, addr, byte_size, - intrin->num_components, bit_size); - } break; }