fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-06 02:58:05 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv/amdgpu: do not check that a CS is aligned if no padding is added

Browse source 
Some video queues don't require padding.

Fixes: d5efbc7f1c ("radv/amdgpu: fix CS padding for non-GFX/COMPUTE queues")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30795>
This commit is contained in:
Samuel Pitoiset 2024-08-22 16:43:20 +02:00 • committed by Marge Bot
parent e3113ffcfd
commit 28c957409f
1 changed files with 5 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
View file

@ -447,23 +447,18 @@ radv_amdgpu_winsys_cs_pad(struct radeon_cmdbuf *_cs, unsigned leave_dw_space)
}
}
} else {
/* Pad the CS with NOP packets. */
bool pad = true;
/* Don't pad on VCN encode/unified as no NOPs */
if (ip_type == AMDGPU_HW_IP_VCN_ENC)
pad = false;
return;
/* Don't add padding to 0 length UVD due to kernel */
if (ip_type == AMDGPU_HW_IP_UVD && cs->base.cdw == 0)
pad = false;
return;
if (pad) {
const uint32_t nop_packet = get_nop_packet(cs);
const uint32_t nop_packet = get_nop_packet(cs);
while (!cs->base.cdw || (cs->base.cdw & pad_dw_mask))
radeon_emit_unchecked(&cs->base, nop_packet);
}
while (!cs->base.cdw || (cs->base.cdw & pad_dw_mask))
radeon_emit_unchecked(&cs->base, nop_packet);
}
assert(((cs->base.cdw + leave_dw_space) & pad_dw_mask) == 0);