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radeonsi: write shader asm annotated with wave info into GPU hang reports
Note that the disassembly is written twice - first the unmodified compiler
output and then the wave-annotated output only if there are waves executing
the shader.
Sample output from a real GPU hang most likely caused by image_sample:
The number of active waves = 28
Pixel Shader - annotated disassembly:
s_mov_b64 s[6:7], exec ; BE86017E [PC=0x10f3e3800, off=0, size=4]
s_wqm_b64 exec, exec ; BEFE077E [PC=0x10f3e3804, off=4, size=4]
...
image_sample v[7:9], v[0:1], s[12:19], s[20:23] dmask:0x7 ; F0800700 00A30700 [PC=0x10f3e3a94, off=660, size=8]
s_buffer_load_dword s20, s[0:3], 0x50 ; C0220500 00000050 [PC=0x10f3e3a9c, off=668, size=8]
s_load_dwordx4 s[24:27], s[4:5], 0x170 ; C00A0602 00000170 [PC=0x10f3e3aa4, off=676, size=8]
s_load_dwordx8 s[12:19], s[4:5], 0x140 ; C00E0302 00000140 [PC=0x10f3e3aac, off=684, size=8]
s_buffer_load_dword s11, s[0:3], 0x5c ; C02202C0 0000005C [PC=0x10f3e3ab4, off=692, size=8]
s_buffer_load_dword s21, s[0:3], 0x54 ; C0220540 00000054 [PC=0x10f3e3abc, off=700, size=8]
s_buffer_load_dword s22, s[0:3], 0x58 ; C0220580 00000058 [PC=0x10f3e3ac4, off=708, size=8]
s_waitcnt vmcnt(0) ; BF8C0F70 [PC=0x10f3e3acc, off=716, size=4]
^ SE0 SH0 CU1 SIMD1 WAVE0 EXEC=aaaaaaa555aaaaaa INST32=BF8C0F70
^ SE0 SH0 CU1 SIMD2 WAVE0 EXEC=aaaa85555555552a INST32=BF8C0F70
^ SE0 SH0 CU1 SIMD3 WAVE0 EXEC=000000000000000a INST32=BF8C0F70
^ SE0 SH0 CU6 SIMD1 WAVE0 EXEC=25a5a5aa82aaaaaa INST32=BF8C0F70
^ SE0 SH0 CU6 SIMD3 WAVE0 EXEC=50aaaa8fffa55555 INST32=BF8C0F70
^ SE0 SH0 CU7 SIMD0 WAVE0 EXEC=5554aaaaaaa1a555 INST32=BF8C0F70
^ SE0 SH0 CU7 SIMD0 WAVE1 EXEC=aaaa5555ffffffff INST32=BF8C0F70
^ SE0 SH0 CU7 SIMD1 WAVE0 EXEC=555557aaaaaaaaa5 INST32=BF8C0F70
^ SE0 SH0 CU7 SIMD3 WAVE0 EXEC=5555aaaaaaaaaa85 INST32=BF8C0F70
^ SE1 SH0 CU3 SIMD1 WAVE0 EXEC=aaaaaaaaaaaaaaaa INST32=BF8C0F70
^ SE1 SH0 CU4 SIMD0 WAVE0 EXEC=aaaaaaaa5a5a5a5a INST32=BF8C0F70
^ SE1 SH0 CU4 SIMD1 WAVE0 EXEC=aaaaaaa5a5a5a4a5 INST32=BF8C0F70
^ SE1 SH0 CU4 SIMD2 WAVE0 EXEC=5555555000000000 INST32=BF8C0F70
^ SE1 SH0 CU4 SIMD3 WAVE0 EXEC=aa555554155aaaaa INST32=BF8C0F70
^ SE1 SH0 CU5 SIMD0 WAVE0 EXEC=55ffff55555555aa INST32=BF8C0F70
^ SE1 SH0 CU5 SIMD1 WAVE0 EXEC=555555555aaaaaaa INST32=BF8C0F70
^ SE1 SH0 CU5 SIMD2 WAVE0 EXEC=a0aaaaaaa8555555 INST32=BF8C0F70
^ SE1 SH0 CU5 SIMD3 WAVE0 EXEC=8aaaaaaaaaaaa555 INST32=BF8C0F70
^ SE1 SH0 CU6 SIMD0 WAVE0 EXEC=000000002aaaaaaa INST32=BF8C0F70
^ SE2 SH0 CU1 SIMD0 WAVE0 EXEC=5aaaa5400aaaa15a INST32=BF8C0F70
^ SE2 SH0 CU1 SIMD1 WAVE0 EXEC=00aaaaaaaa5555aa INST32=BF8C0F70
^ SE2 SH0 CU1 SIMD2 WAVE0 EXEC=aa00005555554555 INST32=BF8C0F70
^ SE2 SH0 CU1 SIMD3 WAVE0 EXEC=aaaaaaa000000000 INST32=BF8C0F70
^ SE3 SH0 CU4 SIMD0 WAVE0 EXEC=5555aaaaaaaaaaaa INST32=BF8C0F70
^ SE3 SH0 CU4 SIMD2 WAVE0 EXEC=ffaaaaaaaaaa5555 INST32=BF8C0F70
^ SE3 SH0 CU4 SIMD3 WAVE0 EXEC=aaaa55555555aa00 INST32=BF8C0F70
^ SE3 SH0 CU5 SIMD0 WAVE0 EXEC=00aaaaaaaaaaaa5a INST32=BF8C0F70
^ SE3 SH0 CU5 SIMD1 WAVE0 EXEC=5a555555005555ff INST32=BF8C0F70
v_mul_f32_e32 v7, s6, v7 ; 0A0E0E06 [PC=0x10f3e3ad0, off=720, size=4]
...
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
parent
3de8c5a3c5
commit
28c06b3ceb
3 changed files with 252 additions and 3 deletions
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@ -468,6 +468,254 @@ static void si_dump_descriptors(struct si_context *sctx,
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num_elements[i], f);
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}
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struct si_shader_inst {
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char text[160]; /* one disasm line */
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unsigned offset; /* instruction offset */
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unsigned size; /* instruction size = 4 or 8 */
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};
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/* Split a disassembly string into lines and add them to the array pointed
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* to by "instructions". */
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static void si_add_split_disasm(const char *disasm,
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uint64_t start_addr,
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unsigned *num,
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struct si_shader_inst *instructions)
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{
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struct si_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL;
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char *next;
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while ((next = strchr(disasm, '\n'))) {
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struct si_shader_inst *inst = &instructions[*num];
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unsigned len = next - disasm;
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assert(len < ARRAY_SIZE(inst->text));
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memcpy(inst->text, disasm, len);
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inst->text[len] = 0;
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inst->offset = last_inst ? last_inst->offset + last_inst->size : 0;
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const char *semicolon = strchr(disasm, ';');
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assert(semicolon);
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/* More than 16 chars after ";" means the instruction is 8 bytes long. */
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inst->size = next - semicolon > 16 ? 8 : 4;
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snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len,
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" [PC=0x%"PRIx64", off=%u, size=%u]",
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start_addr + inst->offset, inst->offset, inst->size);
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last_inst = inst;
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(*num)++;
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disasm = next + 1;
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}
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}
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#define MAX_WAVES_PER_CHIP (64 * 40)
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struct si_wave_info {
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unsigned se; /* shader engine */
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unsigned sh; /* shader array */
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unsigned cu; /* compute unit */
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unsigned simd;
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unsigned wave;
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uint32_t status;
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uint64_t pc; /* program counter */
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uint32_t inst_dw0;
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uint32_t inst_dw1;
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uint64_t exec;
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bool matched; /* whether the wave is used by a currently-bound shader */
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};
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static int compare_wave(const void *p1, const void *p2)
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{
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struct si_wave_info *w1 = (struct si_wave_info *)p1;
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struct si_wave_info *w2 = (struct si_wave_info *)p2;
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/* Sort waves according to PC and then SE, SH, CU, etc. */
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if (w1->pc < w2->pc)
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return -1;
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if (w1->pc > w2->pc)
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return 1;
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if (w1->se < w2->se)
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return -1;
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if (w1->se > w2->se)
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return 1;
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if (w1->sh < w2->sh)
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return -1;
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if (w1->sh > w2->sh)
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return 1;
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if (w1->cu < w2->cu)
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return -1;
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if (w1->cu > w2->cu)
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return 1;
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if (w1->simd < w2->simd)
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return -1;
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if (w1->simd > w2->simd)
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return 1;
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if (w1->wave < w2->wave)
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return -1;
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if (w1->wave > w2->wave)
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return 1;
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return 0;
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}
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/* Return wave information. "waves" should be a large enough array. */
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static unsigned si_get_wave_info(struct si_wave_info waves[MAX_WAVES_PER_CHIP])
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{
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char line[2000];
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unsigned num_waves = 0;
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FILE *p = popen("umr -wa", "r");
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if (!p)
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return 0;
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if (!fgets(line, sizeof(line), p) ||
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strncmp(line, "SE", 2) != 0) {
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pclose(p);
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return 0;
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}
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while (fgets(line, sizeof(line), p)) {
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struct si_wave_info *w;
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uint32_t pc_hi, pc_lo, exec_hi, exec_lo;
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assert(num_waves < MAX_WAVES_PER_CHIP);
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w = &waves[num_waves];
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if (sscanf(line, "%u %u %u %u %u %x %x %x %x %x %x %x",
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&w->se, &w->sh, &w->cu, &w->simd, &w->wave,
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&w->status, &pc_hi, &pc_lo, &w->inst_dw0,
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&w->inst_dw1, &exec_hi, &exec_lo) == 12) {
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w->pc = ((uint64_t)pc_hi << 32) | pc_lo;
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w->exec = ((uint64_t)exec_hi << 32) | exec_lo;
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w->matched = false;
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num_waves++;
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}
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}
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qsort(waves, num_waves, sizeof(struct si_wave_info), compare_wave);
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pclose(p);
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return num_waves;
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}
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/* If the shader is being executed, print its asm instructions, and annotate
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* those that are being executed right now with information about waves that
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* execute them. This is most useful during a GPU hang.
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*/
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static void si_print_annotated_shader(struct si_shader *shader,
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struct si_wave_info *waves,
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unsigned num_waves,
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FILE *f)
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{
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if (!shader || !shader->binary.disasm_string)
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return;
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uint64_t start_addr = shader->bo->gpu_address;
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uint64_t end_addr = start_addr + shader->bo->b.b.width0;
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unsigned i;
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/* See if any wave executes the shader. */
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for (i = 0; i < num_waves; i++) {
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if (start_addr <= waves[i].pc && waves[i].pc <= end_addr)
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break;
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}
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if (i == num_waves)
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return; /* the shader is not being executed */
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/* Remember the first found wave. The waves are sorted according to PC. */
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waves = &waves[i];
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num_waves -= i;
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/* Get the list of instructions.
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* Buffer size / 4 is the upper bound of the instruction count.
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*/
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unsigned num_inst = 0;
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struct si_shader_inst *instructions =
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calloc(shader->bo->b.b.width0 / 4, sizeof(struct si_shader_inst));
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if (shader->prolog) {
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si_add_split_disasm(shader->prolog->binary.disasm_string,
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start_addr, &num_inst, instructions);
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}
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si_add_split_disasm(shader->binary.disasm_string,
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start_addr, &num_inst, instructions);
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if (shader->epilog) {
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si_add_split_disasm(shader->epilog->binary.disasm_string,
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start_addr, &num_inst, instructions);
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}
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fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
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si_get_shader_name(shader, shader->selector->type));
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/* Print instructions with annotations. */
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for (i = 0; i < num_inst; i++) {
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struct si_shader_inst *inst = &instructions[i];
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fprintf(f, "%s\n", inst->text);
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/* Print which waves execute the instruction right now. */
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while (num_waves && start_addr + inst->offset == waves->pc) {
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fprintf(f,
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" " COLOR_GREEN "^ SE%u SH%u CU%u "
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"SIMD%u WAVE%u EXEC=%016"PRIx64 " ",
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waves->se, waves->sh, waves->cu, waves->simd,
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waves->wave, waves->exec);
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if (inst->size == 4) {
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fprintf(f, "INST32=%08X" COLOR_RESET "\n",
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waves->inst_dw0);
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} else {
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fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n",
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waves->inst_dw0, waves->inst_dw1);
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}
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waves->matched = true;
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waves = &waves[1];
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num_waves--;
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}
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}
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fprintf(f, "\n\n");
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free(instructions);
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}
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static void si_dump_annotated_shaders(struct si_context *sctx, FILE *f)
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{
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struct si_wave_info waves[MAX_WAVES_PER_CHIP];
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unsigned num_waves = si_get_wave_info(waves);
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fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
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"\n\n", num_waves);
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si_print_annotated_shader(sctx->vs_shader.current, waves, num_waves, f);
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si_print_annotated_shader(sctx->tcs_shader.current, waves, num_waves, f);
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si_print_annotated_shader(sctx->tes_shader.current, waves, num_waves, f);
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si_print_annotated_shader(sctx->gs_shader.current, waves, num_waves, f);
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si_print_annotated_shader(sctx->ps_shader.current, waves, num_waves, f);
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/* Print waves executing shaders that are not currently bound. */
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unsigned i;
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bool found = false;
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for (i = 0; i < num_waves; i++) {
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if (waves[i].matched)
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continue;
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if (!found) {
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fprintf(f, COLOR_CYAN
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"Waves not executing currently-bound shaders:"
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COLOR_RESET "\n");
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found = true;
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}
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fprintf(f, " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016"PRIx64
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" INST=%08X %08X PC=%"PRIx64"\n",
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waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd,
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waves[i].wave, waves[i].exec, waves[i].inst_dw0,
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waves[i].inst_dw1, waves[i].pc);
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}
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if (found)
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fprintf(f, "\n\n");
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}
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static void si_dump_command(const char *title, const char *command, FILE *f)
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{
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char line[2000];
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@ -502,7 +750,8 @@ static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
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si_dump_shader(sctx->screen, &sctx->ps_shader, f);
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if (flags & PIPE_DUMP_DEVICE_STATUS_REGISTERS) {
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si_dump_command("Active waves", "umr -wa | column -t", f);
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si_dump_annotated_shaders(sctx, f);
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si_dump_command("Active waves (raw data)", "umr -wa | column -t", f);
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si_dump_command("Wave information", "umr -O bits -wa", f);
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}
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@ -5918,8 +5918,7 @@ static void si_shader_dump_stats(struct si_screen *sscreen,
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conf->spilled_vgprs, conf->private_mem_vgprs);
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}
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static const char *si_get_shader_name(struct si_shader *shader,
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unsigned processor)
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const char *si_get_shader_name(struct si_shader *shader, unsigned processor)
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{
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switch (processor) {
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case PIPE_SHADER_VERTEX:
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@ -576,5 +576,6 @@ void si_shader_binary_read_config(struct radeon_shader_binary *binary,
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unsigned symbol_offset);
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unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
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bool writes_samplemask);
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const char *si_get_shader_name(struct si_shader *shader, unsigned processor);
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#endif
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