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iris: Always use BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
Update the clear color with iris rather than with BLORP. This enables an optimization in the next patch. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30824>
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721d0c3e77
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2886851a8e
3 changed files with 54 additions and 43 deletions
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@ -288,31 +288,15 @@ fast_clear_color(struct iris_context *ice,
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PIPE_CONTROL_DATA_CACHE_FLUSH : 0) |
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PIPE_CONTROL_PSS_STALL_SYNC);
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/* From the ICL PRMs, Volume 9: Render Engine, State Caching :
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*
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* "Any values referenced by pointers within the RENDER_SURFACE_STATE
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* [...] (e.g. Clear Color Pointer, [...]) are considered to be part of
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* that state and any changes to these referenced values requires an
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* invalidation of the L1 state cache to ensure the new values are being
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* used as part of the state. [...]"
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*
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* Invalidate the state cache as suggested.
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*/
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if (devinfo->ver >= 11) {
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iris_emit_pipe_control_flush(batch, "fast clear: pre-inval",
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PIPE_CONTROL_STATE_CACHE_INVALIDATE);
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}
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/* Update the clear color now that previous rendering is complete. */
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if (color_changed && res->aux.clear_color_bo)
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iris_resource_update_indirect_color(batch, res);
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iris_batch_sync_region_start(batch);
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/* If we reach this point, we need to fast clear to change the state to
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* ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both).
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*/
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enum blorp_batch_flags blorp_flags = 0;
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blorp_flags |= color_changed ? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR;
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struct blorp_batch blorp_batch;
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blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
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blorp_batch_init(&ice->blorp, &blorp_batch, batch,
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BLORP_BATCH_NO_UPDATE_CLEAR_COLOR);
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struct blorp_surf surf;
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iris_blorp_surf_for_resource(batch, &surf, p_res, res->aux.usage,
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@ -1215,6 +1215,51 @@ iris_render_formats_color_compatible(enum isl_format a, enum isl_format b,
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return false;
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}
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void
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iris_resource_update_indirect_color(struct iris_batch *batch,
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struct iris_resource *res)
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{
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assert(res->aux.clear_color_bo);
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uint32_t pixel[4];
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isl_color_value_pack(&res->aux.clear_color, res->surf.format, pixel);
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iris_emit_pipe_control_write(batch, "update fast clear color (RG____)",
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PIPE_CONTROL_WRITE_IMMEDIATE,
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res->aux.clear_color_bo,
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res->aux.clear_color_offset,
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(uint64_t) res->aux.clear_color.u32[0] |
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(uint64_t) res->aux.clear_color.u32[1] << 32);
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iris_emit_pipe_control_write(batch, "update fast clear color (__BA__)",
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PIPE_CONTROL_WRITE_IMMEDIATE,
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res->aux.clear_color_bo,
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res->aux.clear_color_offset + 8,
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(uint64_t) res->aux.clear_color.u32[2] |
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(uint64_t) res->aux.clear_color.u32[3] << 32);
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iris_emit_pipe_control_write(batch, "update fast clear color (____PX)",
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PIPE_CONTROL_WRITE_IMMEDIATE,
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res->aux.clear_color_bo,
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res->aux.clear_color_offset + 16,
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(uint64_t) pixel[0] |
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(uint64_t) pixel[1] << 32);
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/* From the ICL PRMs, Volume 9: Render Engine, State Caching :
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*
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* "Any values referenced by pointers within the RENDER_SURFACE_STATE
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* [...] (e.g. Clear Color Pointer, [...]) are considered to be part of
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* that state and any changes to these referenced values requires an
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* invalidation of the L1 state cache to ensure the new values are being
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* used as part of the state. [...]"
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*
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* Invalidate the state cache as suggested.
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*/
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iris_emit_pipe_control_flush(batch, "new clear color affects state cache",
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PIPE_CONTROL_FLUSH_ENABLE |
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PIPE_CONTROL_STATE_CACHE_INVALIDATE);
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}
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enum isl_aux_usage
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iris_resource_render_aux_usage(struct iris_context *ice,
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struct iris_resource *res,
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@ -1302,28 +1347,8 @@ iris_resource_prepare_render(struct iris_context *ice,
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if (res->aux.clear_color_bo) {
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/* Update dwords used for rendering and sampling. */
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iris_emit_pipe_control_write(&ice->batches[IRIS_BATCH_RENDER],
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"zero fast clear color (RG____)",
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PIPE_CONTROL_WRITE_IMMEDIATE,
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res->aux.clear_color_bo,
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res->aux.clear_color_offset, 0);
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iris_emit_pipe_control_write(&ice->batches[IRIS_BATCH_RENDER],
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"zero fast clear color (__BA__)",
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PIPE_CONTROL_WRITE_IMMEDIATE,
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res->aux.clear_color_bo,
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res->aux.clear_color_offset + 8, 0);
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iris_emit_pipe_control_write(&ice->batches[IRIS_BATCH_RENDER],
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"zero fast clear color (____PX)",
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PIPE_CONTROL_WRITE_IMMEDIATE,
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res->aux.clear_color_bo,
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res->aux.clear_color_offset + 16, 0);
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iris_emit_pipe_control_flush(&ice->batches[IRIS_BATCH_RENDER],
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"new clear color affects state cache",
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PIPE_CONTROL_FLUSH_ENABLE |
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PIPE_CONTROL_STATE_CACHE_INVALIDATE);
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struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
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iris_resource_update_indirect_color(batch, res);
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} else {
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/* Flag surface states with inline clear colors as dirty. */
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ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
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@ -494,6 +494,8 @@ bool iris_render_formats_color_compatible(enum isl_format a,
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enum isl_format b,
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union isl_color_value color,
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bool clear_color_unknown);
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void iris_resource_update_indirect_color(struct iris_batch *batch,
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struct iris_resource *res);
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enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice,
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struct iris_resource *res,
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enum isl_format render_fmt,
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