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i965: Use ~0 to represent true on all generations.
Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
This commit is contained in:
Matt Turner
parent
05e2578cac
commit
2881b123d0
5 changed files with 120 additions and 102 deletions
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@ -516,18 +516,10 @@ brw_initialize_context_constants(struct brw_context *brw)
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* contains meaning [sic] data, software should make sure all higher bits
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* are masked out (e.g. by 'and-ing' an [sic] 0x01 constant)."
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*
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* We select the representation of a true boolean uniform to match what the
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* CMP instruction returns.
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*
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* The Sandybridge BSpec's description of the CMP instruction matches that
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* of the Ivybridge PRM. (The description in the Sandybridge PRM is seems
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* to have not been updated from Ironlake). Its CMP instruction behaves like
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* Ivybridge and newer.
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* We select the representation of a true boolean uniform to be ~0, and fix
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* the results of Gen <= 5 CMP instruction's with -(result & 1).
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*/
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if (brw->gen >= 6)
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ctx->Const.UniformBooleanTrue = ~0;
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else
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ctx->Const.UniformBooleanTrue = 1;
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ctx->Const.UniformBooleanTrue = ~0;
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/* From the gen4 PRM, volume 4 page 127:
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*
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@ -1399,15 +1399,12 @@ fs_visitor::emit_frontfacing_interpolation()
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* instruction only operates on UD (or D with an abs source modifier)
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* sources without negation.
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*
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* Instead, use ASR (which will give ~0/true or 0/false) followed by an
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* AND 1.
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* Instead, use ASR (which will give ~0/true or 0/false).
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*/
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fs_reg asr = fs_reg(this, glsl_type::bool_type);
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fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D));
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g1_6.negate = true;
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emit(ASR(asr, g1_6, fs_reg(31)));
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emit(AND(*reg, asr, fs_reg(1)));
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emit(ASR(*reg, g1_6, fs_reg(31)));
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}
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return reg;
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@ -535,11 +535,7 @@ fs_visitor::visit(ir_expression *ir)
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switch (ir->operation) {
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case ir_unop_logic_not:
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if (ctx->Const.UniformBooleanTrue != 1) {
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emit(NOT(this->result, op[0]));
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} else {
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emit(XOR(this->result, op[0], fs_reg(1)));
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}
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emit(NOT(this->result, op[0]));
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break;
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case ir_unop_neg:
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op[0].negate = !op[0].negate;
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@ -745,7 +741,7 @@ fs_visitor::visit(ir_expression *ir)
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case ir_binop_all_equal:
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case ir_binop_nequal:
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case ir_binop_any_nequal:
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if (ctx->Const.UniformBooleanTrue == 1) {
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if (brw->gen <= 5) {
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resolve_bool_comparison(ir->operands[0], &op[0]);
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resolve_bool_comparison(ir->operands[1], &op[1]);
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}
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@ -819,16 +815,13 @@ fs_visitor::visit(ir_expression *ir)
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emit(AND(this->result, op[0], fs_reg(1)));
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break;
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case ir_unop_b2f:
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if (ctx->Const.UniformBooleanTrue != 1) {
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op[0].type = BRW_REGISTER_TYPE_D;
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this->result.type = BRW_REGISTER_TYPE_D;
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emit(AND(this->result, op[0], fs_reg(0x3f800000u)));
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this->result.type = BRW_REGISTER_TYPE_F;
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} else {
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temp = fs_reg(this, glsl_type::int_type);
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emit(AND(temp, op[0], fs_reg(1)));
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emit(MOV(this->result, temp));
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if (brw->gen <= 5) {
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resolve_bool_comparison(ir->operands[0], &op[0]);
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}
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op[0].type = BRW_REGISTER_TYPE_D;
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this->result.type = BRW_REGISTER_TYPE_D;
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emit(AND(this->result, op[0], fs_reg(0x3f800000u)));
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this->result.type = BRW_REGISTER_TYPE_F;
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break;
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case ir_unop_f2b:
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@ -2394,39 +2387,36 @@ fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
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break;
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case ir_binop_logic_xor:
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if (ctx->Const.UniformBooleanTrue == 1) {
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fs_reg dst = fs_reg(this, glsl_type::uint_type);
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emit(XOR(dst, op[0], op[1]));
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inst = emit(AND(reg_null_d, dst, fs_reg(1)));
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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if (brw->gen <= 5) {
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fs_reg temp = fs_reg(this, ir->type);
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emit(XOR(temp, op[0], op[1]));
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inst = emit(AND(reg_null_d, temp, fs_reg(1)));
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} else {
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inst = emit(XOR(reg_null_d, op[0], op[1]));
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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}
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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break;
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case ir_binop_logic_or:
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if (ctx->Const.UniformBooleanTrue == 1) {
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fs_reg dst = fs_reg(this, glsl_type::uint_type);
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emit(OR(dst, op[0], op[1]));
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inst = emit(AND(reg_null_d, dst, fs_reg(1)));
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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if (brw->gen <= 5) {
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fs_reg temp = fs_reg(this, ir->type);
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emit(OR(temp, op[0], op[1]));
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inst = emit(AND(reg_null_d, temp, fs_reg(1)));
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} else {
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inst = emit(OR(reg_null_d, op[0], op[1]));
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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}
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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break;
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case ir_binop_logic_and:
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if (ctx->Const.UniformBooleanTrue == 1) {
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fs_reg dst = fs_reg(this, glsl_type::uint_type);
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emit(AND(dst, op[0], op[1]));
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inst = emit(AND(reg_null_d, dst, fs_reg(1)));
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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if (brw->gen <= 5) {
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fs_reg temp = fs_reg(this, ir->type);
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emit(AND(temp, op[0], op[1]));
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inst = emit(AND(reg_null_d, temp, fs_reg(1)));
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} else {
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inst = emit(AND(reg_null_d, op[0], op[1]));
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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}
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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break;
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case ir_unop_f2b:
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@ -2455,7 +2445,7 @@ fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
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case ir_binop_all_equal:
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case ir_binop_nequal:
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case ir_binop_any_nequal:
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if (ctx->Const.UniformBooleanTrue == 1) {
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if (brw->gen <= 5) {
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resolve_bool_comparison(expr->operands[0], &op[0]);
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resolve_bool_comparison(expr->operands[1], &op[1]);
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}
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@ -2545,7 +2535,7 @@ fs_visitor::emit_if_gen6(ir_if *ir)
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case ir_binop_all_equal:
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case ir_binop_nequal:
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case ir_binop_any_nequal:
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if (ctx->Const.UniformBooleanTrue == 1) {
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if (brw->gen <= 5) {
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resolve_bool_comparison(expr->operands[0], &op[0]);
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resolve_bool_comparison(expr->operands[1], &op[1]);
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}
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@ -3412,17 +3402,25 @@ fs_visitor::resolve_ud_negate(fs_reg *reg)
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*reg = temp;
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}
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/**
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* Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
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*
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* CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
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* If we need a proper boolean value, we have to fix it up to be 0 or ~0.
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*/
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void
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fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg)
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{
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assert(ctx->Const.UniformBooleanTrue == 1);
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assert(brw->gen <= 5);
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if (rvalue->type != glsl_type::bool_type)
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return;
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fs_reg temp = fs_reg(this, glsl_type::bool_type);
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emit(AND(temp, *reg, fs_reg(1)));
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*reg = temp;
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fs_reg and_result = fs_reg(this, glsl_type::bool_type);
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fs_reg neg_result = fs_reg(this, glsl_type::bool_type);
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emit(AND(and_result, *reg, fs_reg(1)));
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emit(MOV(neg_result, negate(and_result)));
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*reg = neg_result;
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}
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fs_visitor::fs_visitor(struct brw_context *brw,
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@ -535,6 +535,7 @@ public:
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bool try_emit_mad(ir_expression *ir);
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bool try_emit_b2f_of_compare(ir_expression *ir);
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void resolve_ud_negate(src_reg *reg);
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void resolve_bool_comparison(ir_rvalue *rvalue, src_reg *reg);
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src_reg get_timestamp();
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@ -819,18 +819,36 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
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break;
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case ir_binop_logic_xor:
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inst = emit(XOR(dst_null_d(), op[0], op[1]));
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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if (brw->gen <= 5) {
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src_reg temp = src_reg(this, ir->type);
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emit(XOR(dst_reg(temp), op[0], op[1]));
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inst = emit(AND(dst_null_d(), temp, src_reg(1)));
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} else {
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inst = emit(XOR(dst_null_d(), op[0], op[1]));
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}
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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break;
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case ir_binop_logic_or:
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inst = emit(OR(dst_null_d(), op[0], op[1]));
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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if (brw->gen <= 5) {
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src_reg temp = src_reg(this, ir->type);
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emit(OR(dst_reg(temp), op[0], op[1]));
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inst = emit(AND(dst_null_d(), temp, src_reg(1)));
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} else {
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inst = emit(OR(dst_null_d(), op[0], op[1]));
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}
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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break;
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case ir_binop_logic_and:
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inst = emit(AND(dst_null_d(), op[0], op[1]));
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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if (brw->gen <= 5) {
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src_reg temp = src_reg(this, ir->type);
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emit(AND(dst_reg(temp), op[0], op[1]));
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inst = emit(AND(dst_null_d(), temp, src_reg(1)));
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} else {
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inst = emit(AND(dst_null_d(), op[0], op[1]));
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}
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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break;
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case ir_unop_f2b:
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@ -852,16 +870,27 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
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break;
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case ir_binop_all_equal:
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if (brw->gen <= 5) {
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resolve_bool_comparison(expr->operands[0], &op[0]);
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resolve_bool_comparison(expr->operands[1], &op[1]);
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}
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inst = emit(CMP(dst_null_d(), op[0], op[1], BRW_CONDITIONAL_Z));
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*predicate = BRW_PREDICATE_ALIGN16_ALL4H;
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break;
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case ir_binop_any_nequal:
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if (brw->gen <= 5) {
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resolve_bool_comparison(expr->operands[0], &op[0]);
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resolve_bool_comparison(expr->operands[1], &op[1]);
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}
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inst = emit(CMP(dst_null_d(), op[0], op[1], BRW_CONDITIONAL_NZ));
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*predicate = BRW_PREDICATE_ALIGN16_ANY4H;
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break;
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case ir_unop_any:
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if (brw->gen <= 5) {
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resolve_bool_comparison(expr->operands[0], &op[0]);
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}
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inst = emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
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*predicate = BRW_PREDICATE_ALIGN16_ANY4H;
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break;
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@ -872,6 +901,10 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
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case ir_binop_lequal:
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case ir_binop_equal:
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case ir_binop_nequal:
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if (brw->gen <= 5) {
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resolve_bool_comparison(expr->operands[0], &op[0]);
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resolve_bool_comparison(expr->operands[1], &op[1]);
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}
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emit(CMP(dst_null_d(), op[0], op[1],
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brw_conditional_for_comparison(expr->operation)));
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break;
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@ -902,14 +935,8 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
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resolve_ud_negate(&this->result);
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if (brw->gen >= 6) {
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vec4_instruction *inst = emit(AND(dst_null_d(),
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this->result, src_reg(1)));
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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} else {
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vec4_instruction *inst = emit(MOV(dst_null_d(), this->result));
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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}
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vec4_instruction *inst = emit(AND(dst_null_d(), this->result, src_reg(1)));
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inst->conditional_mod = BRW_CONDITIONAL_NZ;
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}
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/**
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@ -1322,11 +1349,7 @@ vec4_visitor::visit(ir_expression *ir)
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switch (ir->operation) {
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case ir_unop_logic_not:
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if (ctx->Const.UniformBooleanTrue != 1) {
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emit(NOT(result_dst, op[0]));
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} else {
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emit(XOR(result_dst, op[0], src_reg(1)));
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}
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emit(NOT(result_dst, op[0]));
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break;
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case ir_unop_neg:
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op[0].negate = !op[0].negate;
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@ -1512,11 +1535,12 @@ vec4_visitor::visit(ir_expression *ir)
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case ir_binop_gequal:
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case ir_binop_equal:
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case ir_binop_nequal: {
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if (brw->gen <= 5) {
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resolve_bool_comparison(ir->operands[0], &op[0]);
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resolve_bool_comparison(ir->operands[1], &op[1]);
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}
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emit(CMP(result_dst, op[0], op[1],
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brw_conditional_for_comparison(ir->operation)));
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if (ctx->Const.UniformBooleanTrue == 1) {
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emit(AND(result_dst, result_src, src_reg(1)));
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}
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break;
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}
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@ -1530,9 +1554,6 @@ vec4_visitor::visit(ir_expression *ir)
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inst->predicate = BRW_PREDICATE_ALIGN16_ALL4H;
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} else {
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emit(CMP(result_dst, op[0], op[1], BRW_CONDITIONAL_Z));
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if (ctx->Const.UniformBooleanTrue == 1) {
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emit(AND(result_dst, result_src, src_reg(1)));
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}
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}
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break;
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case ir_binop_any_nequal:
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@ -1546,9 +1567,6 @@ vec4_visitor::visit(ir_expression *ir)
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inst->predicate = BRW_PREDICATE_ALIGN16_ANY4H;
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} else {
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emit(CMP(result_dst, op[0], op[1], BRW_CONDITIONAL_NZ));
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if (ctx->Const.UniformBooleanTrue == 1) {
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emit(AND(result_dst, result_src, src_reg(1)));
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}
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}
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break;
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@ -1610,28 +1628,22 @@ vec4_visitor::visit(ir_expression *ir)
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emit(MOV(result_dst, op[0]));
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break;
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case ir_unop_b2i:
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if (ctx->Const.UniformBooleanTrue != 1) {
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emit(AND(result_dst, op[0], src_reg(1)));
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} else {
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emit(MOV(result_dst, op[0]));
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}
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emit(AND(result_dst, op[0], src_reg(1)));
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break;
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case ir_unop_b2f:
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if (ctx->Const.UniformBooleanTrue != 1) {
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op[0].type = BRW_REGISTER_TYPE_D;
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result_dst.type = BRW_REGISTER_TYPE_D;
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emit(AND(result_dst, op[0], src_reg(0x3f800000u)));
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result_dst.type = BRW_REGISTER_TYPE_F;
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} else {
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emit(MOV(result_dst, op[0]));
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if (brw->gen <= 5) {
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resolve_bool_comparison(ir->operands[0], &op[0]);
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}
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op[0].type = BRW_REGISTER_TYPE_D;
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result_dst.type = BRW_REGISTER_TYPE_D;
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emit(AND(result_dst, op[0], src_reg(0x3f800000u)));
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result_dst.type = BRW_REGISTER_TYPE_F;
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break;
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case ir_unop_f2b:
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case ir_unop_i2b:
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emit(CMP(result_dst, op[0], src_reg(0.0f), BRW_CONDITIONAL_NZ));
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if (ctx->Const.UniformBooleanTrue == 1) {
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emit(AND(result_dst, result_src, src_reg(1)));
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}
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break;
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case ir_unop_i2b:
|
||||
emit(AND(result_dst, op[0], src_reg(1)));
|
||||
break;
|
||||
|
||||
case ir_unop_trunc:
|
||||
|
|
@ -1777,9 +1789,6 @@ vec4_visitor::visit(ir_expression *ir)
|
|||
if (ir->type->base_type == GLSL_TYPE_BOOL) {
|
||||
emit(CMP(result_dst, packed_consts, src_reg(0u),
|
||||
BRW_CONDITIONAL_NZ));
|
||||
if (ctx->Const.UniformBooleanTrue == 1) {
|
||||
emit(AND(result_dst, result, src_reg(1)));
|
||||
}
|
||||
} else {
|
||||
emit(MOV(result_dst, packed_consts));
|
||||
}
|
||||
|
|
@ -3535,6 +3544,27 @@ vec4_visitor::resolve_ud_negate(src_reg *reg)
|
|||
*reg = temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
|
||||
*
|
||||
* CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
|
||||
* If we need a proper boolean value, we have to fix it up to be 0 or ~0.
|
||||
*/
|
||||
void
|
||||
vec4_visitor::resolve_bool_comparison(ir_rvalue *rvalue, src_reg *reg)
|
||||
{
|
||||
assert(brw->gen <= 5);
|
||||
|
||||
if (!rvalue->type->is_boolean())
|
||||
return;
|
||||
|
||||
src_reg and_result = src_reg(this, rvalue->type);
|
||||
src_reg neg_result = src_reg(this, rvalue->type);
|
||||
emit(AND(dst_reg(and_result), *reg, src_reg(1)));
|
||||
emit(MOV(dst_reg(neg_result), negate(and_result)));
|
||||
*reg = neg_result;
|
||||
}
|
||||
|
||||
vec4_visitor::vec4_visitor(struct brw_context *brw,
|
||||
struct brw_vec4_compile *c,
|
||||
struct gl_program *prog,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue