From 287f7a9c355aef4a46ed21ef9de41e02ee106dc3 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Sat, 5 Aug 2023 20:30:05 +0800 Subject: [PATCH] radeonsi: set vs has prolog aco shader info MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Marek Olšák Signed-off-by: Qiang Yu Part-of: --- src/gallium/drivers/radeonsi/si_shader_aco.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader_aco.c b/src/gallium/drivers/radeonsi/si_shader_aco.c index 41829e6f6bd..a25c507af1f 100644 --- a/src/gallium/drivers/radeonsi/si_shader_aco.c +++ b/src/gallium/drivers/radeonsi/si_shader_aco.c @@ -87,6 +87,16 @@ si_fill_aco_shader_info(struct si_shader *shader, struct aco_shader_info *info, } switch (stage) { + case MESA_SHADER_VERTEX: + /* Only part mode VS may have prolog, mono mode VS will embed prolog in nir. + * But we don't know exactly if part mode VS needs prolog because it also depends + * on shader select key ls_vgpr_fix which is not known when VS main part compile. + * Now just assume ls_vgpr_fix is always false, which just cause ACO to add extra + * s_setprio and exec init code when it's finally combined with prolog. + */ + if (!shader->is_gs_copy_shader && !shader->is_monolithic) + info->vs.has_prolog = si_vs_needs_prolog(sel, &key->ge.part.vs.prolog); + break; case MESA_SHADER_TESS_CTRL: info->vs.tcs_in_out_eq = key->ge.opt.same_patch_vertices; info->vs.tcs_temp_only_input_mask = sel->info.tcs_vgpr_only_inputs;