From 2874160ce24c9d0899bb01ebca04eddbe0bbb25b Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Thu, 22 Jan 2026 13:21:24 -0800 Subject: [PATCH] brw: Call nir_opt_algebraic_late in brw_nir_create_raygen_trampoline Make sure that lowering undone in brw_nir_optimize are reapplied. No shader-db changes on any Intel platform. Why are there fossil-db changes on platforms that don't support ray tracing? Lunar Lake Totals: Instrs: 926636441 -> 926636313 (-0.00%); split: -0.00%, +0.00% Send messages: 41510729 -> 41510723 (-0.00%); split: -0.00%, +0.00% Cycle count: 104509492613 -> 104509490569 (-0.00%); split: -0.00%, +0.00% Max live registers: 193792922 -> 193792890 (-0.00%); split: -0.00%, +0.00% Non SSA regs after NIR: 150091934 -> 150092170 (+0.00%); split: -0.00%, +0.00% Totals from 10 (0.00% of 2020428) affected shaders: Instrs: 8142 -> 8014 (-1.57%); split: -3.14%, +1.57% Send messages: 192 -> 186 (-3.12%); split: -7.29%, +4.17% Cycle count: 131892 -> 129848 (-1.55%); split: -6.93%, +5.38% Max live registers: 1442 -> 1410 (-2.22%); split: -3.05%, +0.83% Non SSA regs after NIR: 950 -> 1186 (+24.84%); split: -26.95%, +51.79% Meteor Lake Totals: Instrs: 1000805547 -> 1000805543 (-0.00%); split: -0.00%, +0.00% Cycle count: 93131592265 -> 93131619619 (+0.00%); split: -0.00%, +0.00% Max live registers: 122081268 -> 122081244 (-0.00%); split: -0.00%, +0.00% Totals from 16 (0.00% of 2286241) affected shaders: Instrs: 18652 -> 18648 (-0.02%); split: -1.39%, +1.37% Cycle count: 369520 -> 396874 (+7.40%); split: -2.94%, +10.34% Max live registers: 1350 -> 1326 (-1.78%); split: -4.15%, +2.37% DG2 Totals: Instrs: 999834626 -> 999834651 (+0.00%); split: -0.00%, +0.00% Send messages: 45719398 -> 45719403 (+0.00%); split: -0.00%, +0.00% Cycle count: 93118238139 -> 93118269557 (+0.00%); split: -0.00%, +0.00% Max live registers: 122098944 -> 122098936 (-0.00%); split: -0.00%, +0.00% Non SSA regs after NIR: 169413734 -> 169413661 (-0.00%); split: -0.00%, +0.00% Totals from 13 (0.00% of 2286795) affected shaders: Instrs: 18799 -> 18824 (+0.13%); split: -1.04%, +1.18% Send messages: 492 -> 497 (+1.02%); split: -2.44%, +3.46% Cycle count: 352838 -> 384256 (+8.90%); split: -1.08%, +9.98% Max live registers: 1237 -> 1229 (-0.65%); split: -2.91%, +2.26% Non SSA regs after NIR: 2191 -> 2118 (-3.33%); split: -20.86%, +17.53% Tiger Lake Totals: Instrs: 1011816778 -> 1011816714 (-0.00%); split: -0.00%, +0.00% Send messages: 46515289 -> 46515285 (-0.00%); split: -0.00%, +0.00% Cycle count: 85148902406 -> 85148894668 (-0.00%); split: -0.00%, +0.00% Max live registers: 122362180 -> 122362172 (-0.00%); split: -0.00%, +0.00% Max dispatch width: 38036160 -> 38036176 (+0.00%) Non SSA regs after NIR: 160317521 -> 160317649 (+0.00%); split: -0.00%, +0.00% Totals from 6 (0.00% of 2282318) affected shaders: Instrs: 9204 -> 9140 (-0.70%); split: -1.43%, +0.74% Send messages: 258 -> 254 (-1.55%); split: -3.10%, +1.55% Cycle count: 287652 -> 279914 (-2.69%); split: -3.29%, +0.60% Max live registers: 552 -> 544 (-1.45%); split: -2.90%, +1.45% Max dispatch width: 48 -> 64 (+33.33%) Non SSA regs after NIR: 914 -> 1042 (+14.00%); split: -14.00%, +28.01% Ice Lake Totals: Instrs: 1012203285 -> 1012203249 (-0.00%); split: -0.00%, +0.00% Send messages: 47358859 -> 47358858 (-0.00%); split: -0.00%, +0.00% Cycle count: 85112165276 -> 85112171905 (+0.00%); split: -0.00%, +0.00% Max live registers: 125545002 -> 125544992 (-0.00%); split: -0.00%, +0.00% Max dispatch width: 41335696 -> 41335656 (-0.00%) Non SSA regs after NIR: 166448597 -> 166448602 (+0.00%); split: -0.00%, +0.00% Totals from 13 (0.00% of 2335519) affected shaders: Instrs: 16486 -> 16450 (-0.22%); split: -1.67%, +1.46% Send messages: 368 -> 367 (-0.27%); split: -4.89%, +4.62% Cycle count: 347643 -> 354272 (+1.91%); split: -1.34%, +3.25% Max live registers: 1104 -> 1094 (-0.91%); split: -3.80%, +2.90% Max dispatch width: 192 -> 152 (-20.83%) Non SSA regs after NIR: 2100 -> 2105 (+0.24%); split: -21.76%, +22.00% Skylake Totals: Instrs: 504548665 -> 504548057 (-0.00%); split: -0.00%, +0.00% Send messages: 24479148 -> 24479118 (-0.00%); split: -0.00%, +0.00% Cycle count: 57575198140 -> 57575179256 (-0.00%); split: -0.00%, +0.00% Max live registers: 85570671 -> 85570575 (-0.00%); split: -0.00%, +0.00% Non SSA regs after NIR: 85097646 -> 85098486 (+0.00%); split: -0.00%, +0.00% Totals from 22 (0.00% of 1703671) affected shaders: Instrs: 19866 -> 19258 (-3.06%); split: -3.72%, +0.66% Send messages: 464 -> 434 (-6.47%); split: -8.19%, +1.72% Cycle count: 250854 -> 231970 (-7.53%); split: -9.23%, +1.70% Max live registers: 2024 -> 1928 (-4.74%); split: -5.53%, +0.79% Non SSA regs after NIR: 2498 -> 3338 (+33.63%); split: -8.33%, +41.95% Fixes: 442daeb54a2 ("nir/opt_algebraic: use fcanonicalize") Reviewed-by: Alyssa Rosenzweig (cherry picked from commit 5af0b8bd09f6e07d9a069ddbd93eeffd90ba1906) Part-of: --- .pick_status.json | 2 +- src/intel/compiler/brw/brw_nir_rt.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/.pick_status.json b/.pick_status.json index d8912d8f477..c979b836ccf 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -4524,7 +4524,7 @@ "description": "brw: Call nir_opt_algebraic_late in brw_nir_create_raygen_trampoline", "nominated": true, "nomination_type": 2, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "442daeb54a2e43bd450ebbb37fc05001f4acd08f", "notes": null diff --git a/src/intel/compiler/brw/brw_nir_rt.c b/src/intel/compiler/brw/brw_nir_rt.c index e54d6431364..8eef9f6e2d3 100644 --- a/src/intel/compiler/brw/brw_nir_rt.c +++ b/src/intel/compiler/brw/brw_nir_rt.c @@ -518,6 +518,8 @@ brw_nir_create_raygen_trampoline(const struct brw_compiler *compiler, NIR_PASS(_, nir, brw_nir_lower_cs_intrinsics, devinfo, NULL); brw_nir_optimize(nir, devinfo); + /* brw_nir_optimize undoes late lowerings. */ + NIR_PASS(_, nir, nir_opt_algebraic_late); return nir; }