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radeonsi: flush VGT streamout like PAL

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Ported from 165b016bbe.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>
This commit is contained in:
Pierre-Eric Pelloux-Prayer 2022-04-11 16:25:01 +02:00
parent 1126f42781
commit 283730f368
1 changed files with 8 additions and 1 deletions
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9
src/gallium/drivers/radeonsi/si_state_streamout.c
View file

@ -283,7 +283,14 @@ static void si_flush_vgt_streamout(struct si_context *sctx)
radeon_begin(cs);
/* The register is at different places on different ASICs. */
if (sctx->chip_class >= GFX7) {
if (sctx->chip_class >= GFX9) {
reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
radeon_emit(PKT3(PKT3_WRITE_DATA, 3, 0));
radeon_emit(S_370_DST_SEL(V_370_MEM_MAPPED_REGISTER) | S_370_ENGINE_SEL(V_370_ME));
radeon_emit(R_0300FC_CP_STRMOUT_CNTL >> 2);
radeon_emit(0);
radeon_emit(0);
} else if (sctx->chip_class >= GFX7) {
reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
radeon_set_uconfig_reg(reg_strmout_cntl, 0);
} else {