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synced 2026-05-04 22:49:13 +02:00
freedreno/a4xx: use generic clear path
Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
f77e59e76c
commit
27f12dd8fd
2 changed files with 4 additions and 215 deletions
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@ -54,7 +54,7 @@ fd4_context_destroy(struct pipe_context *pctx)
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fd_context_destroy(pctx);
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}
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static const uint8_t primtypes[PIPE_PRIM_MAX] = {
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static const uint8_t primtypes[] = {
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[PIPE_PRIM_POINTS] = DI_PT_POINTLIST,
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[PIPE_PRIM_LINES] = DI_PT_LINELIST,
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[PIPE_PRIM_LINE_STRIP] = DI_PT_LINESTRIP,
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@ -62,6 +62,7 @@ static const uint8_t primtypes[PIPE_PRIM_MAX] = {
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[PIPE_PRIM_TRIANGLES] = DI_PT_TRILIST,
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[PIPE_PRIM_TRIANGLE_STRIP] = DI_PT_TRISTRIP,
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[PIPE_PRIM_TRIANGLE_FAN] = DI_PT_TRIFAN,
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[PIPE_PRIM_MAX] = DI_PT_RECTLIST, /* internal clear blits */
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};
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struct pipe_context *
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@ -131,9 +131,8 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
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.vclamp_color = ctx->rasterizer->clamp_vertex_color,
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.fclamp_color = ctx->rasterizer->clamp_fragment_color,
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.rasterflat = ctx->rasterizer->flatshade,
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// TODO set .half_precision based on render target format,
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// ie. float16 and smaller use half, float32 use full..
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.half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
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.half_precision = ctx->in_blit &&
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fd_half_precision(&ctx->batch->framebuffer),
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.ucp_enables = ctx->rasterizer->clip_plane_enable,
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.has_per_samp = (fd4_ctx->fsaturate || fd4_ctx->vsaturate ||
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fd4_ctx->fastc_srgb || fd4_ctx->vastc_srgb),
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@ -193,220 +192,9 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
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return true;
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}
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/* clear operations ignore viewport state, so we need to reset it
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* based on framebuffer state:
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*/
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static void
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reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
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{
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float half_width = pfb->width * 0.5f;
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float half_height = pfb->height * 0.5f;
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OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 4);
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OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(half_width));
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OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(half_width));
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OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(half_height));
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OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-half_height));
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}
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/* TODO maybe we should just migrate u_blitter for clear and do it in
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* core (so we get normal draw pass state mgmt and binning).. That should
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* work well enough for a3xx/a4xx (but maybe not a2xx?)
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*/
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static void
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fd4_clear_binning(struct fd_context *ctx, unsigned dirty)
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{
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struct fd_ringbuffer *ring = ctx->batch->binning;
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struct fd4_emit emit = {
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.debug = &ctx->debug,
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.vtx = &ctx->solid_vbuf_state,
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.prog = &ctx->solid_prog,
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.key = {
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.binning_pass = true,
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.half_precision = true,
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},
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.dirty = dirty,
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};
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fd4_emit_state(ctx, ring, &emit);
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fd4_emit_vertex_bufs(ring, &emit);
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reset_viewport(ring, &ctx->batch->framebuffer);
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OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
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OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_VAROUT(0) |
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A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
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OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
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A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES));
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OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
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OUT_RING(ring, 0x00000002);
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fd4_draw(ctx->batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
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DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
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}
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static void
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fd4_clear(struct fd_context *ctx, unsigned buffers,
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const union pipe_color_union *color, double depth, unsigned stencil)
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{
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struct fd_ringbuffer *ring = ctx->batch->draw;
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struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
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unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
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unsigned dirty = ctx->dirty;
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unsigned i;
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struct fd4_emit emit = {
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.debug = &ctx->debug,
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.vtx = &ctx->solid_vbuf_state,
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.prog = &ctx->solid_prog,
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.key = {
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.half_precision = fd_half_precision(pfb),
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},
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};
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dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
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dirty |= FD_DIRTY_PROG;
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emit.dirty = dirty;
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fd4_clear_binning(ctx, dirty);
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OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
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OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
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/* emit generic state now: */
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fd4_emit_state(ctx, ring, &emit);
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reset_viewport(ring, pfb);
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if (buffers & PIPE_CLEAR_DEPTH) {
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OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
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OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
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A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
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A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
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fd_wfi(ctx->batch, ring);
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OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0, 2);
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OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
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OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(depth));
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ctx->dirty |= FD_DIRTY_VIEWPORT;
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} else {
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OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
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OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
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}
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if (buffers & PIPE_CLEAR_STENCIL) {
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OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
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OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(stencil) |
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A4XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
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A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
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OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
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A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
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0xff000000 | // XXX ???
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A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
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OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
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OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
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A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
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A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
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A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
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A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
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A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
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A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
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A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
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A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
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OUT_RING(ring, A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER);
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} else {
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OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
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OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
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A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
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A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
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OUT_RING(ring, A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
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A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
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A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
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OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
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OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
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A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
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A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
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A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
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A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
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A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
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A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
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A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
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OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
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}
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if (buffers & PIPE_CLEAR_COLOR) {
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OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
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OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
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}
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for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
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mrt_comp[i] = (buffers & (PIPE_CLEAR_COLOR0 << i)) ? 0xf : 0x0;
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OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
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OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
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A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
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OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
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OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
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A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
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A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
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A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
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A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
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A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
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}
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OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
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OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
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A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
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A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
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A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
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A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
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A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
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A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
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A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
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fd4_emit_vertex_bufs(ring, &emit);
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OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
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OUT_RING(ring, 0x0); /* XXX GRAS_ALPHA_CONTROL */
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OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
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OUT_RING(ring, 0x00000000);
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/* until fastclear works: */
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fd4_emit_const(ring, SHADER_FRAGMENT, 0, 0, 4, color->ui, NULL);
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OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
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OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
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OUT_RING(ring, 0); /* ??? UNKNOWN_2209 */
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OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
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OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
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OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
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OUT_RING(ring, 0x00000001);
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fd4_draw(ctx->batch, ring, DI_PT_RECTLIST, USE_VISIBILITY,
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DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
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OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
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OUT_RING(ring, 0x00000000);
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OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
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OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
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OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
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OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
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A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
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A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
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A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
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}
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void
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fd4_draw_init(struct pipe_context *pctx)
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{
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struct fd_context *ctx = fd_context(pctx);
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ctx->draw_vbo = fd4_draw_vbo;
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ctx->clear = fd4_clear;
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}
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