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freedreno/layout: Don't align explicit layouts to page size

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This could cause importing buffers, in particular multiplanar YUV, since
when the offset of the plane is added, the aligned size could be beyond
the end of the buffer.

Fixes: 27b0f64b3e ("freedreno/a6xx: Use handle for explicit layout")
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36656>
(cherry picked from commit 8c59aacc10)
This commit is contained in:
Rob Clark 2025-08-07 15:09:45 -07:00 • committed by Eric Engestrom
parent 025c9553dc
commit 27df52f558
3 changed files with 2 additions and 13 deletions
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2
.pick_status.json
View file

@ -5364,7 +5364,7 @@
"description": "freedreno/layout: Don't align explicit layouts to page size",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "27b0f64b3ed04c7ebf98405cd5515af44be9ee24",
"notes": null

11
src/freedreno/ci/freedreno-a618-fails.txt
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@ -226,17 +226,6 @@ spec@arb_base_instance@arb_base_instance-drawarrays,Fail
spec@ext_base_instance@arb_base_instance-baseinstance-doesnt-affect-gl-instance-id_gles3,Fail
spec@ext_base_instance@arb_base_instance-drawarrays_gles3,Fail
# Bad assumptions in piglit about layout of multiplanar formats,
# it should use separate buffers per plane:
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-export,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_nv12,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_nv21,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_p010,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_p012,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_p016,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_yuv420,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_yvu420,Fail
# Regression from https://gitlab.freedesktop.org/mesa/mesa/-/compare/ace49d9e52a6156f114ee00eec759d734bd84fc0...88c79a13b9056099048080e7d41576e0cb69c347
spec@glsl-1.50@execution@variable-indexing@vs-output-array-vec2-index-wr-before-gs,Fail
spec@glsl-1.50@execution@variable-indexing@vs-output-array-vec3-index-wr-before-gs,Fail

2
src/freedreno/fdl/fd6_layout.c
View file

@ -317,7 +317,7 @@ fdl6_layout_image(struct fdl_layout *layout, const struct fd_dev_info *info,
}
}
if (layout->layer_first) {
if (layout->layer_first && !explicit_layout) {
layout->layer_size = align64(layout->size, 4096);
layout->size = layout->layer_size * params->array_size;
}