diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 128005317ed..a69f6d09864 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -1308,7 +1308,7 @@ radv_image_reset_layout(struct radv_image *image)
 	image->size = 0;
 	image->alignment = 1;
 
-	image->tc_compatible_cmask = image->tc_compatible_htile = 0;
+	image->tc_compatible_cmask = 0;
 	image->fce_pred_offset = image->dcc_pred_offset = 0;
 	image->clear_value_offset = image->tc_compat_zrange_offset = 0;
 
@@ -1381,9 +1381,6 @@ radv_image_create_layout(struct radv_device *device,
 	image->tc_compatible_cmask = radv_image_has_cmask(image) &&
 	                             radv_use_tc_compat_cmask_for_image(device, image);
 
-	image->tc_compatible_htile = radv_image_has_htile(image) &&
-	                             image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
-
 	radv_image_alloc_values(device, image);
 
 	assert(image->planes[0].surface.surf_size);
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 7b36238a96a..c5b6979d8a2 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1904,7 +1904,6 @@ struct radv_image {
 	/* Set when bound */
 	struct radeon_winsys_bo *bo;
 	VkDeviceSize offset;
-	bool tc_compatible_htile;
 	bool tc_compatible_cmask;
 
 	uint64_t clear_value_offset;
@@ -2031,7 +2030,8 @@ radv_htile_enabled(const struct radv_image *image, unsigned level)
 static inline bool
 radv_image_is_tc_compat_htile(const struct radv_image *image)
 {
-	return radv_image_has_htile(image) && image->tc_compatible_htile;
+	return radv_image_has_htile(image) &&
+	       (image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE);
 }
 
 /**